In 64-bit mode, there are limitations on accessing byte registers. An instruction cannot reference legacy high-bytes (for example: AH, BH, CH, DH) and one of the new byte registers at the same time (for example: the low byte of the RAX register). However, instructions may reference legacy low-bytes (for example: AL, BL, CL or
DL) and new byte registers at the same time (for example: the low byte of the R8 register, or RBP). The architecture enforces this limitation by changing high-byte refere阅读全文>
发表于 @ 2007年01月04日 17:25:00|评论(loading...)|编辑
3.3.7.1 Canonical Addressing
In 64-bit mode, an address is considered to be in canonical form if address bits 63
through to the most-significant implemented bit by the microarchitecture are set to
either all ones or all zeros.
Intel 64 architecture defines a 64-bit linear address. Implementations can support
less. The first implementation of IA-32 processors with Intel 64 architecture supports
a 48-bit linear address. This means a canonical address must have bits 63 through 48
set to zero阅读全文>
发表于 @ 2007年01月04日 16:09:00|评论(loading...)|编辑