基于VHDL的层次化设计：异步清零和同步使能4位十六进制加法计数器和七段显示译码器的元件例化实现

-----------------------------------------------------------------------------------------------方案一----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------（本实现方案只编写了一个vhdl文件，计数器和译码器的vhdl描述写在了一个文件里。本文件包含三个实体：分别是计数器counter4，译码器decoder，以及一个顶层实体HIERARCHIC，顶层文件里实现了计数器和译码器的结合。）

方案一源程序如下：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY HIERARCHIC IS
  PORT(CP,R,EN:IN STD_LOGIC;
       CO:OUT STD_LOGIC;
       LED:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END HIERARCHIC;
ARCHITECTURE HI OF HIERARCHIC IS
SIGNAL SIGN1:STD_LOGIC_VECTOR(3 DOWNTO 0);
COMPONENT COUNTER4
  PORT(CP,R,EN:IN STD_LOGIC;
       CO:OUT STD_LOGIC;
       Q:BUFFER STD_LOGIC_VECTOR(3 DOWNTO0));
END COMPONENT;
COMPONENT DECODER
  PORT(Ain:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       LED:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END COMPONENT;
BEGIN
U1:COUNTER4 PORT MAP(CP,R,EN,CO,SIGN1);
U2:DECODER PORT MAP(SIGN1,LED);
END HI;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNTER4 IS
  PORT(CP,R,EN:IN STD_LOGIC;
       Q:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
       CO:OUT STD_LOGIC);
END COUNTER4;               
ARCHITECTURE COUNT OF COUNTER4 IS
BEGIN
  PROCESS(CP,R)
  BEGIN
    IF(R='1')THEN Q<="0000";
    ELSIF(CP'EVENT AND CP='1'AND EN='1')THEN
      IF(Q="1111")THEN Q<="0000";
      ELSE Q<=Q+1;
      END IF;
    END IF;
  END PROCESS;
  CO<='1'WHEN Q=15 AND EN='1'ELSE'0';
END COUNT;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECODER IS
  PORT(Ain:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       LED:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END DECODER;      
ARCHITECTURE DECODE OF DECODER IS
SIGNAL SIGN2:STD_LOGIC_VECTOR(6 DOWNTO 0);