端口（Port）

端口（Port）

模块和所属环境之间动态通信的通道。
A channel for dynamic communication between a block and its environment.

语法（Syntax）

port ( 端口名, ... : [ 模式 ] 数据类型 [ := 设定值 ] );

模式 = in | out | inout | buffer | linkage

port ( port_name, ... : [ mode ] data_type [ := Expression ] );

mode = in | out | inout | buffer | linkage

说明（Description）

端口表示一个硬件元件的一个管脚或者一组相关联的管脚。
A port represents a pin or a related group of pins on a hardware component.

在技术上来说，一个端口就是一个信号。
A port is, technically, a signal.

五种不同的模式定义如下：
The five different modes have the following definitions:

• in 输入端口。这种端口只读。不允许给它赋值。
• in input port. This port can only be read. It is not allowed to assign a value to it.
• out 输出端口。这种端口只能被赋值。不允许读取它。
• out output port. This port can only be assigned. It is not allowed to read from it.
• inout 双向端口。这种端口既允许读取亦能赋值。
• inout bi-directional port. Both assignments to such a port and reading from it are allowed.
• buffer 带有读取功能的输出端口。它不同于inout的是端口的值仅能由一个源来更新，但是inout的值可以被零或多个源来更新。
• buffer output port with read capability. It differs from inout in that it can be updated by at most one source, whereas inout can be updated by zero or more sources.
• linkage。端口的值可以被读取或者更新，但仅根据与其先关联的接口模式来实现一个模式。
• linkage. The value of the port may be read or updated, but only by appearing as an actual corresponding to an interface object of mode linkage.

例程（Example）

port (Clk, Rst: in std_logic;
D: in std_logic_vector(3 downto 0);
Status: out std_logic;
Q: buffer std_logic_vector(3 downto 0);

注释（Note）

• 端口定义等同于信号定义，所以端口信号没必要重复定义。
•  Port declarations are signal declarations and port signals need not to be re-declared.