<rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:trackback="http://madskills.com/public/xml/rss/module/trackback/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/"><channel><title>陈硕的Blog - Digital Circuit Design with Verilog</title><link>http://blog.csdn.net/solstice/category/153521.aspx</link><description /><dc:language>zh-CN</dc:language><lastUpdateTime>Fri, 15 Feb 2008 18:10:00 GMT</lastUpdateTime><ttl>60</ttl><item><dc:creator>陈硕</dc:creator><title>用Bresenham算法在FPGA上实现小数分频器</title><link>http://blog.csdn.net/solstice/archive/2005/12/12/549965.aspx</link><pubDate>Mon, 12 Dec 2005 09:33:00 GMT</pubDate><guid>http://blog.csdn.net/solstice/archive/2005/12/12/549965.aspx</guid><wfw:comment>http://blog.csdn.net/solstice/comments/549965.aspx</wfw:comment><comments>http://blog.csdn.net/solstice/archive/2005/12/12/549965.aspx#Feedback</comments><slash:comments>6</slash:comments><wfw:commentRss>http://blog.csdn.net/solstice/comments/commentRss/549965.aspx</wfw:commentRss><trackback:ping>http://tb.blog.csdn.net/TrackBack.aspx?PostId=549965</trackback:ping><description>&lt;img src ="http://blog.csdn.net/solstice/aggbug/549965.aspx" width = "1" height = "1" /&gt;</description></item><item><dc:creator>陈硕</dc:creator><title>Verilog与C++的类比</title><link>http://blog.csdn.net/solstice/archive/2005/11/24/536283.aspx</link><pubDate>Thu, 24 Nov 2005 12:09:00 GMT</pubDate><guid>http://blog.csdn.net/solstice/archive/2005/11/24/536283.aspx</guid><wfw:comment>http://blog.csdn.net/solstice/comments/536283.aspx</wfw:comment><comments>http://blog.csdn.net/solstice/archive/2005/11/24/536283.aspx#Feedback</comments><slash:comments>3</slash:comments><wfw:commentRss>http://blog.csdn.net/solstice/comments/commentRss/536283.aspx</wfw:commentRss><trackback:ping>http://tb.blog.csdn.net/TrackBack.aspx?PostId=536283</trackback:ping><description>&lt;img src ="http://blog.csdn.net/solstice/aggbug/536283.aspx" width = "1" height = "1" /&gt;</description></item><item><dc:creator>陈硕</dc:creator><title>关于在FPGA上实现AES算法的笔记</title><link>http://blog.csdn.net/solstice/archive/2005/10/21/510864.aspx</link><pubDate>Fri, 21 Oct 2005 13:05:00 GMT</pubDate><guid>http://blog.csdn.net/solstice/archive/2005/10/21/510864.aspx</guid><wfw:comment>http://blog.csdn.net/solstice/comments/510864.aspx</wfw:comment><comments>http://blog.csdn.net/solstice/archive/2005/10/21/510864.aspx#Feedback</comments><slash:comments>0</slash:comments><wfw:commentRss>http://blog.csdn.net/solstice/comments/commentRss/510864.aspx</wfw:commentRss><trackback:ping>http://tb.blog.csdn.net/TrackBack.aspx?PostId=510864</trackback:ping><description>&lt;img src ="http://blog.csdn.net/solstice/aggbug/510864.aspx" width = "1" height = "1" /&gt;</description></item></channel></rss>