Verilog任意整数分频器

Verilog任意整数分频器

在实际设计中有的时候需要简单的任意整数分频器，整数分频器主要解决两种情况下的分频，一个是偶数分频，另一个是奇数分频

偶数分频

偶数分频比较简单，可以使用一个计数器来实现，对输入时钟进行计数，当计数器的值为N/2-1时，将输出翻转，同时将计数器清零即可。（N为分频系数）

module EvenDiv_v100(
N,
fin,
rst,
fout
);


input [4:0] N;
input fin,rst;

output reg fout;


reg [4:0] cnter;
always @(posedge fin or posedge rst)
begin
 if(rst) 
  begin
   cnter<=5'd0;
   fout<=1'b0;
  end
 else if(cnter>=({1'b0,N[4:1]}-1))
  begin
   cnter<=5'd0;
   fout<=~fout;
  end
 else
  cnter<=cnter+5'd1;
end

endmodule

奇数分频

奇数分频稍微复杂一些，针对需要输出为50%占空比的情况下，要采用两个计数器分别对输入时钟的上升沿和下降沿计数，计数到(N-1)/2时对输出进行翻转，继续计数到N-1的时候对输出进行再次翻转同时清空计数器，将两个计数器（分别是上升沿和下降沿）输出结果相或输出即可。

module OddDiv_v100(
N,
fin,
rst,
fout

);

input [4:0] N;
input fin,rst;

output wire fout; assign fout=PosOut|NegOut;

reg [4:0] PosCnter,NegCnter;
reg PosOut,NegOut;

always @(posedge fin or posedge rst)
begin
 if(rst)
  begin
   PosOut<=1'b0;
   PosCnter<=5'd0;
  end
 else if(PosCnter==(N-1)/2)
  begin
   PosCnter<=PosCnter+5'd1;
   PosOut<=~PosOut;
  end
 else if(PosCnter==(N-1))
  begin
   PosCnter<=5'd0;
   PosOut<=~PosOut;
  end
 else
  PosCnter<=PosCnter+5'd1;
end

always @(negedge fin or posedge rst)
begin
 if(rst)
  begin
   NegCnter<=5'd0;
   NegOut<=1'b0;
  end
 else if(NegCnter==(N-1)/2)
  begin
   NegCnter<=NegCnter+5'd1;
   NegOut<=~NegOut;
  end
 else if(NegCnter==(N-1))
  begin
   NegCnter<=5'd0;
   NegOut<=~NegOut;
  end
 else
  NegCnter<=NegCnter+5'd1;
end

endmodule

两种情况结合一下

将上述对奇数和偶数分频逻辑集合一下，可以直接判定输入分频系数N为奇数或偶数来决定输出奇数分频结果或者偶数分频结果

module FrequencyDivision_v100(
N,
fin,
rst,
fout
);

input [4:0] N;

input fin,rst;

output wire fout; assign fout=N[0]?OddFout:EvenFout;


reg [4:0] EvenCnter,OddCnter1,OddCnter2;
reg EvenFout,OddFout1,OddFout2;

wire OddFout; assign OddFout=OddFout1|OddFout2;

//==============Even Frequency Division===========//
always @(posedge fin or posedge rst)
begin
 if(rst)
  begin
   EvenCnter<=5'd0;
   EvenFout<=1'b0;
  end
 else if(EvenCnter>=({1'b0,N[4:1]}-1))
  begin
   EvenCnter<=5'd0;
   EvenFout<=~EvenFout;
  end
 else
  EvenCnter<=EvenCnter+5'd1;
end

//==============Odd Frequency Division===========//
always @(posedge fin or posedge rst)
begin
 if(rst)
  begin
   OddFout1<=1'b0;
   OddCnter1<=5'd0;
  end
 else if(OddCnter1==(N-1)/2)
  begin
   OddCnter1<=OddCnter1+5'd1;
   OddFout1<=~OddFout1;
  end
 else if(OddCnter1==(N-1))
  begin
   OddCnter1<=5'd0;
   OddFout1<=~OddFout1;
  end
 else
  OddCnter1<=OddCnter1+5'd1;
end

always @(negedge fin or posedge rst)
begin
 if(rst)
  begin
   OddCnter2<=5'd0;
   OddFout2<=1'b0;
  end
 else if(OddCnter2==(N-1)/2)
  begin
   OddCnter2<=OddCnter2+5'd1;
   OddFout2<=~OddFout2;
  end
 else if(OddCnter2==(N-1))
  begin
   OddCnter2<=5'd0;
   OddFout2<=~OddFout2;
  end
 else
  OddCnter2<=OddCnter2+5'd1;
end


endmodule