转载 2007年09月17日 20:09:00

ISO 7816(1-3) Smart Card Standard(二)

ISO7816 3.2.c - Deactivation of the contacts

When informations exchange is terminated or aborted (unresponsive card or detection of card removal), the electrical contacts shall be desactivated.

The deactivation by the interface device shall consist of the consecutive operations:

- State L on RST;
- State L on CLK;
- Vpp inactive;
- State A on I/O;
- VCC inactive;

ISO7816 3.3 Answer to Reset

Two types of transmissions are considered:

* Asynchronous transmission:
In this type of transmission, characters are transmitted on the I/O line in an asynchronous half duplex mode. Each character includes an 8bit byte.

* Synchronous transmission:
In this type of transmission, a series of bits is transmitted on the I/O line in half duplex mode in synchronisation with the clock signal on CLK.

ISO7816 3.1.a - Answer to Reset in asynchronous transmission

* Bit duration
The nominal bit duration used on I/O is defined as one Elementary Time Unit (etu).

For cards having internal clock, the initial etu is 1/9600 s.

For cards using the external clock, there is a linear relationship between the Elementary Time Unit used on I/O and the period provided by the interface device on CLK.

The initial etu is 372/fi s where fi is in Hertz.

The initial frequency fi is provided by the interface device on CLK during the Answer to Reset.

In order to read the initial character (TS), all cards shall initially be operated with fi in the range of 1 MHz to 5 MHz.

* Character frame during answer to reset
Prior to the transmission of a character, I/O shall be in state Z.

A character consists of ten consecutive bits:

- a start bit in state A;
- eight bits of information, designated ba to bh and conveying a data byte;
- a tenth bit bi used for even parity checking.

A data byte consists of 8 bits designated b1 to b8, from the least significant bit (lsb, b1) to the most significant bit (msb, b8).

Conventions (level coding, connecting levels Z/A to digits 1 or 0: and a bit significance, connecting to b1...b8) are specified in the initial character, call TS, which is transmitted by the card in response to reset.

Parity is correct when the number of ONES is even in the sequence from ba to bi.

Whithin a character, the time from the leading edge of the start bit to the trailing edge of the nth bit shall equal (n+/-0.2) etu.

When searching for a start, the receiver samples I/O periodically. The time origin being the mean between last observation of level Z and first observation of level A, the start shall be verified before 0.7 etu, and then ba is received at (1.5 +/-0.2) etu. Parity is checked on the fly.

NOTE : When searching for a start, the sampling time shall be less than 0.2 etu so that all the test zones are distinct from the transition zones.

The delay between two consecutives characters (between start leading edges) is at least 12 etu, including a character duration (10+/-0.2) etu plus a guardtime, the interface device and the card reamain both in reception, so that I/O is in state Z.

            Start                          Parity             Next
             bit <----- 8 data bits -----> bit              Start bit
     Z   ____     ________________________________......______     __
             |   |  |  |  |  |  |  |  |  |  |                 |   |
     I/O     |   |ba|bb|bc|bd|be|bf|bg|bh|bi|     Guardtime   |   |
             |___|__|__|__|__|__|__|__|__|__|                 |___|_
     A       :   :                    :     :
             0   t1                   :    t10
             :                        :
             :<---- (n+/-0.2) etu --->:

                          Figure 3: Character frame

During the Answer to Reset, the delay between the start leading edges of two consecutives characters from the card shall not exeed 9600 etu. This maximum is named initial waiting time.

* Error detection and character repetition
During the answer to reset, the following characters repetition procedure depends on the protocol type. This procedure is mandatory for cards using the protocol type T=0; it is optional for the interface device and for the other cards.

The transmitter tests I/O (11+/-0.2) etu after the start leading edge:
- If I/O is in state Z, the correct reception is assumed.
- If I/O is in state A, the transmission is assumed to have been incorrect. The disputed character shall be repeated after a delay of at least 2 etu after detection of the error signal.

When parity is incorrect, from (10.5+/-0.2) etu, the receiver transmits an error signal at state A for 1 etu minimum and 2 etu maximum. The receiver then shall expect a repetition of the disputed character (see figure 8).

If no character repetition is provided by the card, - The card ignores and shall not suffer damage from the error signal coming from the interface device.
- The interface device shall be able to initiate the reception and the whole Answer to Reset response sequence.

* Structures and content
A reset operation results in the answer from the card consisting of the initial character TS followed by at most 32 characters in the following order:

         - T0 ................... Format character     (Mandatory)
         - TAi, TBi, TCi, TDi ... Interface characters  (Optional)
         - T1, T2, ... ,TK ...... Historical characters (Optional)
         - TCK .................. Check character    (Conditional)

 |    _________________________________________         _______   _________
 |   |   |   |   |   |   |   |   |   |   |   |           |   |     |   |   |
 '-->| TS| T0|TA1|TB1|TC1|TD1|TA2|TB2|TC2|TD2| ......... | T1| ... | TK|TCK|
     |___|___|___|___|___|___|___|___|___|___|_         _|___|_   _|__ |___|

     TS  : Initial character
     TO  : Format character
     TAi : Interface character [ codes FI,DI ]
     TBi : Interface character [ codes II,PI1 ]
     TCi : Interface character [ codes N ]
     TDi : Interface character [ codes Yi+1, T ]
     T1, ... , TK : Historical characters (max,15)
     TCK : Check character

         Figure 4 : General configuration of the Answer to Reset

The interface characters specify physical parameters of the integrated circuit in the card and logical characteristics of the subsequent exchange protocol.

The historical characters designate general information, for example, the card manufacturer, the chip inserted in the card, the masked ROM in the chip, the state of the life of the card. The specification of the historical characters falls outside the scope of this part of ISO/IEC7816.

For national simplicity, T0, TAi, ... ,TCK will designate the bytes as well as the characters in which they are contained.

Structure of TS, the initial character
The initial character TS provides a bit shynchronisation sequence and defines the conventions to code data bytes in all subsequent characters. These conventions refer to ISO1177.

I/O is initially in state Z. A bit synchronisation sequence (Z)AZZA is defined for the start bit and bits ba bb bc (see figure 5).

The last 3 bits bg bh bi shall be AAZ for checking parity.

NOTE : This allows the interface device to determinate the etu initially used by the card. An alternate measurement of etu is a third of the delay between the first two falling edges in TS. Transmission and reception mechanisms in the card shall be consistent with the alternate
definition of etu.

The two possible values of TS (ten consecutive bits from start to bi and corresponding hexadecimal value) are

- Inverse convention : (Z)ZZAAAAAZ
where logic level ONE is A, ba is b8 (msb is first), equal to $3F when decoded by inverse convention.

- Direct convention : (Z)ZZAZZZAAZ
where logic level ONE is Z, ba is b1 (lsb first), equal to $3B when decoded by direct convention.

                 Start  ba  bb  bc  bd  be  bf  bg  bh  bi
          Z   ____     _______     ___________         ______
                  |   |   |   |   | Z   Z   Z |       |       |   |
               (Z)| A | Z   Z | A |     or    |       | Z  (Z)
          A       |___|       |___|_A___A___A_|___|___|

                    Figure 5 : Initial character TS

Structure of the subsequent characters in the Answer to Reset
The initial character TS is followed by a variable number of subsequent characters in the following order: The format character T0 and, optionally the interface characters TAi, TBi, TCi, TDi and the
historical characters T1, T2, ... , TK and conditionally, the check character TCK.

The presence of the interface characters is indicated by a bit map technique explained below.

The presence of the historical characters is indicated by the number of bytes as specified in the format character defined below.

The presence of the check character TCK depends on the protocol type(s) as defined as below.

- Format character T0
The T0 character contains two parts:

- The most significant half byte (b5, b6, b7, b8) is named Y1 and indicates with a logic level ONE the presence of subsequent characters TA1, TB1, TC1, TD1 respectively.

- The least significant half byte (b4 to b1) is named K and indicates the number (0 to 15) of historical characters.

         | b8 | b7 | b6 | b5 | b4 | b3 | b2 | b1 |
         :<------- Y1 ------>:<-------- K ------>:

         Y1 : indicator for the presence of the interface characters
                TA1 is transmitted when b5=1
                TB1 is transmitted when b6=1
                TC1 is transmitted when b7=1
                TD1 is transmitted when b8=1

         K : number of hitorical characters

                    Figure 6 : Informations provided by T0

- Interface characters TAi, TBi, TCi, TDi

TAi, TBi, TCi (i=1, 2, 3, ... ) indicate the protocol parameters.
TDi indicates the protocol type T and the presence of subsequent

Bits b5, b6, b7, b8 of the byte containing Yi (T0 contains Y1; TDi contains Yi+1) state whelther character TAi for b5, character TBi for b6, character TCi for b7, character TDi for b8 are or are not (depending on whether the relevant bit is 1 or 0) transmitted subsequently in this
order after the character containing Yi.

When needed, the interface device shall attribute a default value to information corresponding to a non transmitted interface character.

When TDi is not transmitted, the default value of Yi+1 is null, indicating that no further interface characters TAi+j, TBi+j, TCi+j, TDi+j will be transmitted.

         | b8 | b7 | b6 | b5 | b4 | b3 | b2 | b1 |
         :<------ Yi+1 ----->:<------- T ------->:

         Yi+1 : indicator for the presence of the interface characters
                TAi+1 is transmitted when b5=1
                TBi+1 is transmitted when b6=1
                TCi+1 is transmitted when b7=1
                TDi+1 is transmitted when b8=1

         T : Protocol type for subsequent transmission.

                    Figure 7 : Informations provided by TDi

- Historical characters T1, T2, ... ,TK

When K is not null, the answer to reset is continued by transmitting K historical characters T1, T2, ... , TK.

- Check character TCK

The value of TCK shall be such that the exclusive-oring of all bytes from T0 to TCK included is null.

The answer to reset is complete 12 etu after the leading edge of the last character.

Protocol type T
The four least significant bits of any interface character TDi indicate a protocol type T, specifying rules to be used to process transmission protocols. When TDi is not transmitted, T=0 is used.

T=0 is the asynchronous half duplex character transmission protocol.
T=1 is the asynchronous half duplex block transmission protocol.
T=2 and T=3 are reserved for future full duplex operations.
T=4 is reserved for an enhanced asynchronous half duplex character
transmission protocol.
T=5 to T=13 are reserved for future use.
T=14 is reserved for protocols standardized by ISO.
T=15 is reserved for future extension.

NOTE : If only T=0 is indicated, TCK shall not be sent. In all other cases TCK shall be sent.

Specifications of the global interface bytes
Among the interface bytes possibly transmitted by the card in answering to reset, this subclaus defines only the global interface bytes TA1,TB1, TC1, TD1.

These global interface bytes convey information to determine parameters which the interface device shall take into account.

- Parameters F, D, I, P, N

This initial etu is used during answer to reset is replaced by the work etu during subsequent transmission. F is the clock rate conversion factor and D is the bit rate adjustment factor to determine the work etu in subsequent transmissions.

For internal clock cards:

initial etu = 1/9600 s work etu = (1/D)*(1/9600) s

For external clock cards:

initial etu = 372/fi s work etu = (1/D)*(F/fs) s

The minimum value of fs shall be 1MHz.
The maximum value of fs is given by table 6.

I and P define the active state at VPP.
- Maximum programming current : Ipp = 1mA
- Programming voltage : Vpp = P.V

N is an extra guardtime requested by the card. Before receiving the next character, the card requires a delay of at least (12+N) etu from the start leading edge of the previous character. No extra guardtme is used to send characters from the card to the interface device.

The default values of these parameters are:
F = 372 ; D = 1 ; I = 50 ; P = 5 ; N = 0

- Integer values in global interface bytes

The global interface bytes, TA1, TB1, TC1, TB2 code integer values FI, DI II, PI1, N, PI2 which are either equal to or used to compute the values of the parameters F, D, I, P, N presented above.

TA1 codes FI over the most significant half byte (b8 to b5) and DI over the least significant half byte (b4 to b1).

TB1 codes II over the bits b7 and b6, and PI1 over the 5 least significant bits b5 to b1. The most significant bit b8 equals to 0.

NOTE : The interface device may ignore the bit b8 of TB1.

TC1 codes N over the eight bits (b8 to b1).

TB2 codes PI2 over the eight bits (b8 to b1).

Table 6: Clock rate conversion factor F

            FI     |     0000      0001  0010  0011  0100  0101  0110  0111
            F      | Internal clk   372   558   744  1116  1488  1860  RFU
      fs (max) MHz |      -           5     6     8    12    16    20   -

            FI     | 1000  1001  1010  1011  1100  1101  1110  1111
            F      |  RFU   512   768  1024  1536  2048   RFU  RFU
      fs (max) MHz |  -       5   7.5    10    15    20    -    -
      RFU : Reserved for Future Use

     Table 7: Bit rate afjustment factor D

        DI | 0000  0001  0010  0011  0100  0101  0110  0111
        D  |  RFU     1     2     4     8    16   RFU   RFU

        DI | 1000  1001  1010  1011  1100  1101  1110  1111
        D  |  RFU   RFU   1/2   1/4   1/8  1/16  1/32  1/64
      RFU : Reserved for Future Use

- Programming voltage factor P

PI1 from 5 to 25 gives the value of P in volts. PI1=0 indicates that VPP is connected in the card which generates an internal programming voltage from VCC. Other values of PI1 are reserved for future use.

When PI2 is present, the indication of PI1 should be ignores. PI2 from 50 to 250 gives the value of P in 0.1V. Other values of PI2 are reserved for future use.

Table 8 : Maximum programming current factor I
      II  |   00    01    10    11
      I   |   25    50   100   RFU

- Extra guardtime N

N codes directly the extra guard time, from 0 to 254 etu. N=255 indicates that the minimum delay between the start edges of two consecutives characters is reduced to 11 etu.

ISO 7816(1-3) Smart Card Standard(一)

Part1: Physical Charcteristics of Integrated Circuit Cards

This part describes the physical charcteristics of integrated circuit cards. It includes accomodation of exposure limits for a number of electromagnetic phenomena such as X-rays, UV light, elacromagnetic fields, static electrical fields, and ambient temperature of the card.

Furthermore ISO7816-1 defines the characteristics of a card when it is bent or flexed. This is to make sure that plastic cards with embedded chips are manufactured in a way that guarantees flawless operation over the expected life time of a card. Connections beween the surface connectors and the I/O pins of the embedded silicon die must be maintaned and withstand mechanical stress. Bending and flexing procedures are standardised in ISO 7816.

This part of ISO7816 is important for card manufacturers. They are the ones that choose the materials and establish a process that embeds the integrated circuit into the card.

Part 2: Dimensions and Location of the Contacts

ISO 7816 part 2 defines the dimensions and location of the contacts. This part includes standards about number, function and position of the electrical contacts.

The integrated circuit card (ICC) has 8 electrical contacts . They are referred to as C1 through C8. However, not all 8 contacts are electrically connected to the embedded microprocessor chip and therefore unused at the present time.

The following table contains the contact definition according to ISO7816-2

Contact Designation Use
C1 Vcc Power connection through which operating power is supplied to the microprocessor chip in the card
C2 RST Reset line through which the IFD can signal to the smart card's microprocessor chip to initiate its reset sequence of instructions
C3 CLK Clock signal line t hrough which a clock signal can be provided to the microprocessor chip. This line controls the operation speed and provides a common framework for data communication between the IFD and the ICC
C4 RFU Reserved for future use
C5 GND Ground line providing common electrical ground between the IFD and the ICC
C6 Vpp Programming power connection used to program EEPROM of first generation ICCs.
C7 I/O Input/output line that provides a half-duplex communication channel between the reader and the smart card
C8 RFU Reserved for future use


Some smart cards issued before 1990 were adherent to a different standard for the contact location and therefore can't be used with today's ISO7816-2 compliant smart card readers. These cards were deployed primarily in Europe.


Part 3: Electronic Signals and Transmission Protocols (1)

This part describes electronic signals and transmission protocols of integrated circuit cards. We copied it from a version that is available on the Internet. If you need the official version of this part, please contact ISO in switzerland.. If you have suggestions or material to include (tables, graphs etc) please contact us. The document will stay at this location for anyone that wants a direct link to this part of the standard. We will edit this document shortly, bring it up to date and add comments.

Most of ISO7816 3 is important for reader manufacturers or developers who want to establish a communication with a smart card on a very low level, the signal level. Going through ISO 7816-3 you will see what's involved in writing your own I/O software. This can be either to communicate from a microcontroller or a PC's serial/parallel/USB/PCMCIA port. Even if you don't go that far, it is quite interesting to read about what you can get out of an Answer to Reset (ATR).

There are many tools out there to read an ATR. Even on this site we put a remote version of a free ATR probing tool that reads and interprets an ATR over the Internet. All you need is a PCSC compliant smart card reader attached to a PC with an Internet connection.

Electrical Signals Description

I/O : Input or Output for serial data to the integrated circuit inside the card.

VPP : Programing voltage input (optional use by the card).

GND : Ground (reference voltage).

CLK : Clocking or timing signal (optional use by the card).

RST : Either used itself (reset signal supplied from the interface device) or in combination with an interal reset control circuit (optional use by the card). If internal reset is implemented, the voltage
supply on Vcc is mandatory.

VCC : Power supply input (optional use by the card).

NOTE - The use of th two remaining contacts will be defined in the appropriate application standards.

ISO7816 3.1 Voltage and current values


Vih : High level input voltage
Vil : Low level input voltage
Vcc : Power supply voltage at VCC
Vpp : Programming voltage at VPP
Voh : High level output voltage
Vol : Low level output voltage
tr : Rise time between 10% and 90% of signal amplitude
tf : Fall time between 90% and 10% of signal amplitude
Iih : High level input current
Iil : Low level input current
Icc : Supply current at VCC
Ipp : Programming current at VPP
Ioh : High level output current
Iol : Low level output current
Cin : Input capacitance
Cout: Output capacitance

* I/O

This contact is used as input (reception mode) or output (transmission mode) for data exchange. Two possible states exist for I/O:

- mark or high state (State Z), if the card and the interface device are in reception mode or if the state is imposed by the transmitter.

- space or low state (State A), if this state is imposed by the

When the two ends of the line are in reception mode, the line shall be maintained in state Z. When the two ends are in non-matced transmit mode, the logic state of the line may be indeterminate. During operations, the interface device and the card shall not both be in transmit mode.

Table 1 - Electrical characteristics of I/O under normal operation conditions.

| Symbol |          Conditions            | Minimum | Maximum | Unit |
|        | Either | Iih max = +/- 500uA   |    2    |    VCC  |   V  |
|  Vih   |   (1)  +-----------------------+---------+---------+------+
|        |   or   | Iih max = +/- 50uA    | 0.7 VCC | VCC (3) |   V  |
|  Vil   |          Iil max = 1mA         |    0    |    0.8  |   V  |
|        | Either | Iol max = +/- 100uA   |   2.4   |    VCC  |   V  |
|  Voh   |        +-----------------------+---------+---------+------+
|    (2) |   or   | Iol max = +/- 20uA    |   3.8   |    VCC  |   V  |
|  Vol   |          Iol max = 1mA         |    0    |    0.4  |   V  |
| tr, tf | Cin = 30pF;   Cout = 30pF      |         |      1  |   us |
| (1) For the interface device, take into account both conditions.   |
| (2) It is assumed that a pull up resistor is used in the interface |
|     device (recommended value 20k Ohm.                             |
| (3) The voltage on I/O shall remain between 0.3V and VCC+0.3V.     |

This contact may be to supply the voltage required to program or to erase the internal non-volatile memory. Two possible states exists for VPP: Idle state and active state, as defined in table 2. The idle state shall be maintained by the interface device unless the active state is required.

Table 2 : Electrical characteristics of VPP under normal operation conditions.

| Symbol |          Conditions            | Minimum | Maximum | Unit |
|  Vpp   |         Idle State             | 0.95*Vcc| 1.05*Vcc|   V  |
|  Ipp   |   (programming non active)     |         |   20    |  mA  |
|  Vpp   |        Active State            | 0.975*P | 1.025*P |   V  |
|  Ipp   |    (programming the card)      |         |     I   |  mA  |
| The card provides the interface with the values of P and I         |
| (default values: P=5 and I=50)                                     |

Rise of fall time : 200 us maximum. The rate of change of Vpp shall not exceed 2V/us.
The maximum power Vpp*Ipp shall not exceed 1.5W when averaged over any period of 1s.


The actual frequency, delivered by the interface device on CLK, is designated either by fi the initial frequency during the answer to reset, or by fs the subsequent frequency during subsequent transmission.

Duty cycle for asynchronous operations shall be between 45% and 55% of the period during stable operation. Care shall be taken when switching frequencies (from fi to fs) to ensure that no pulse is shorter than 45% of the shorter period.

Table 3 - Electrical characteristics of CLK under normal operation conditions.

     | Symbol |          Conditions            | Minimum | Maximum | Unit |
     |        | Either | Iih max = +/- 200uA   |   2.4   | VCC (2) |   V  |
     |        |   (1)  +-----------------------+---------+---------+------+
     |  Vih   |   or   | Iih max = +/- 20uA    | 0.7*VCC | VCC (2) |   V  |
     |        |   (1)  +-----------------------+---------+---------+------+
     |        |   or   | Iih max = +/- 10uA    | VCC-0.7 | VCC (2) |   V  |
     |  Vil   |          Iil max = +/-200 uA   |   0 (2) |    0.5  |   V  |
     | tr, tf |          Cin = 30pF            |         |9% of the period|
     |        |                                |         |with a max:0.5us|
     | (1) For the interface device, take into account three conditions.  |
     | (2) The voltage on CLK shall remain between 0.3V and Vcc+0.3V.     |


Table 4 - Electrical characteristics of RST under normal operation conditions.

     | Symbol |          Conditions            | Minimum | Maximum | Unit |
     |        | Either | Iih max = +/- 200uA   |    4    | VCC (2) |   V  |
     |  Vih   |   (1)  +-----------------------+---------+---------+------+
     |        |   or   | Iih max = +/- 10uA    | VCC-0.7 | VCC (2) |   V  |
     |  Vil   |          Iil max = +/- 200uA   |   0 (2) |    0.6  |   V  |
     | (1) For the interface device, take into account both conditions.   |
     | (2) The voltage on RST shall remain between 0.3V and VCC+0.3V.     |


This contact is used to supply the power voltage Vcc.

Table 5 - Electrical characteristics of VCC under normal operation conditions.

              | Symbol | Minimum | Maximum |  Unit |
              |  Vcc   |   4.75  |   5.25  |   V   |
              |  Icc   |         |    200  |  mA   |

ISO7816 3.2 Operating procedure for integrated circuit(s) cards

This operating procedure applies to every integrated circuit(s) card with contacts:

The dialogue between the interface device and the the card shall be conducted through the consecutive operations:

- connection and activation of the contacts by the interface device.
- reset of the card.
- answer to reset by the card.
- subsequent information exchange between the card and the interface device.
- desactivation of the contacts by the interface device.

These operations are specified in the following subclauses.

An active state on VPP should not only be provided and maintained when requested by the card.

ISO7816 3.2.a - Connection and activation of the contacts

The electrical circuits shall not be activated until the contacts are connected to the interface device so as to avoid possible damage to any card meeting these standards.

The activation of the contacts by the interface device shall consist of the consecutive operations:

- RST is in state L;
- VCC shall be powered;
- I/O in the interface device shall be put in reception mode;
- VPP shall be raised to idle state;
- CLK shallbe provided with a suitable and stable clock.

ISO7816 3.2.b - Reset of the card

A card reset is initiated by the interface device, whereupon the card shall respond with an Answer to Reset as describe in 2.4.

By the end of the activation of the contacts (RST is in L, VCC powered and stable, I/O in reception mode in the interface device, VPP stable at idle level, CLK provided with a suitable and stable clock), the card answering asynchronously is ready for reset.

The clock signal is applied to CLK at time T0. The I/O line shall be set to state Z within 200 clcok cycles of the clock signal (t2) being applied to CLK (time t2 after T0).

An internally reset card reset after a few cycles of clock signal. The Answer to Reset on I/O shall begin between 400 and 40 000 clock cycles (t1) after the clock signal is applied to CLK (time t1 after T0).

A card with an active low reset is reset by maintaining RST in state L for at least 40 000 clock cycles (t3) after the clock signal is applied on CLK (time t3 after T0). Thus if no Answer to Reset begind within 40 000 clock cycles (t3) with RST in state L, RST is put to state H (at time T1). The
Answer to Reset on I/O shall begin between 400 and 40 000 clock cycles (t1) after the rising edge of the signal on RST (time t1 after T1).

If the Anwser to Reset does not begin within 40 000 clock cycles (t3) with RST in state H (t3 after T1), the signal on RST shall be returned to state L (at time T2) and the contacts shall be desactivated by the interface device.

GND ________________________________________________________________________
VCC _| :                                                               :|___
VPP __|:                                                               |____
       :             t3                            t3                  :
       :                             :_________________________________:
RST ___:_____________________________|                                 |____
       :                             :                                 :
CLK ___|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||____
       :       t1                    :                                 :
       :<-------------->:            :                                 :
       :      __________:____________:_________________________________:
I/O __XXXXXXXX          |____________:_______Answer____________________:XXXX
(IR)   :      :                      :                                 :
       :  t2  :                      :      t1                         :
       :<---->:                      :<---------->:                    :
       :      _______________________:_________________________________:
I/O __XXXXXXXX                       :            |______Answer________:XXXX
(AL)   :  t2  :                      :                                 :
       :<---->:                      :                                 :
       :                             :_________________________________:
I/O __XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX:                                 :XXXXX
(SH)   :                             :                                 :
       T0                            T1                                T2
       IR : Internal Reset                t2 <= 200/fi
  AL : Asynchronous Reset            400/fi <= t1 <= 40000/fi
  SH : Syncronous Reset              40000/fi <= t3

                      Figure1 : Reset of the card

With a card answering synchonously, the interface device sets all the lines to state L (See figure 2). VCC is the powered, VPP is set to idle state, CLK and RST remain in L state, I/O is put in reception mode in the interface device, RST shall be maintained in state H for at least 50 us (t12), before returning to state L again.

The clock pulse is applied after an interval (t10) from the rising edge of the reset signal. The duration of the state H of the clock pulse can be any value between 10 us and 50 us ; no more than one clock pulse during reset high is allowed. The time interval between the falling edges on CLK
and RST is t11.

The first data bit is obtained as an answer to reset on I/O while CLK is in state L and is valid after an interval t13 from the falling edge on RST.


RST_____/:                   /_______________________________________________
         :                    :
         :  t10           t11 :          t15      t16
         :<---->:      :<---->:  t14   :<---->: :<---->:
                : ____ :      :<---->: :______: :      : _______
CLK_____________:/  1 /:______:______:/   2    /:______:/   3   /_______
                              :                 :
                              : t13             :  t17
                              :<---->:          :<---->:
       _____________________________ :______________   :______________   ___

5us  <= t10                          10us <= t14 <= 100us Clock low after RST
5us  <= t11                          10us <= t15 <= 50us  Clock High
50us <= t12 ........ Reset High      10us <= t16 <= 100us Clock Low
t13  <= 10us  Propagation delay      t17 <= 10us  Propagation delay

           Figure2 : Reset of the card when a synchronous answer is expected.


1 - The internal state of the card is assumed not to be defined before reset. Therefore the design of the card has to avoid inproper operation.

2 - In order to continue the dialogue with the card, RST shall be maintained in the state where an answer occurs on I/O.

3 - Reset of a card can be initiated by the interface device at its discetion at any time.

4 - Interface devices may support one or more of these types of reset behaviour. The priority of testing for asynchronous or synchronous cards is not defined in this standard.


随着 Ic卡从简单的同步卡发展到异步卡,从简单的 EPROM卡发展到内带微处理器的智能卡(又称CPU卡),对IC卡的各种要求越来越高。而卡本身所需要的各种管理工作也越来越复杂,因此就迫切地需要有一种工具来解决这一矛盾,而内部带有微处理器的智能卡的出现,使得这种工具的实现变成了现实。人们利用它内部的微处理器芯片,开发了应用于智能卡内部的各种各样的操作系统,也就是在本节将要论述的COS。 COs的出现不仅大大地改善了智能卡的交互界面,使智能卡的管理变得容易;而且,更为重要的是使智能卡本身向着个人计算机化的方向迈出了一大步,为智能卡的发展开拓了极为广阔的前景。
1 COS概述
COS的全称是Chip Operating System(片内操作系统),它一般是紧紧围绕着它所服务的智能卡的特点而开发的。由于不可避免地受到了智能卡内微处理器芯片的性能及内存容量的影响,因此,COS在很大程度上不同于我们通常所能见到的微机上的操作系统(例如DOS、UNIX等)。首先,COS是一个专用系统而不是通用系统。即:一种COS一般都只能应用于特定的某种(或者是某些)智能卡,不同卡内的COS一般是不相同的。因为coS一般都是根据某种智能卡的特点及其应用范围而特定设计开发的,尽管它们在所实际完成的功能上可能大部分都遵循着同一个国际标准。其次,与那些常见的微机上的操作系统相比较而言,COS在本质上更加接近于监控程序、而不是一个通常所谓的真正意义上的操作系统,这一点至少在目前看来仍是如此。因为在当前阶段,COS所需要解决的主要还是对外部的命令如何进行处理、响应的问题,这其中一般并不涉及到共享、并发的管理及处理,而且就智能卡在目前的应用情况而盲,并发和共享的工作也确实是不需要曲。COS在设计时一般都是紧密结合智能卡内存储器分区的情况,按照国际标准(ISO/IEC7816系列标准)中所规定的一些功能进行设计、开发。但是由于目前智能卡的发展速度很快,而国际标准的制定周期相对比较长一些,因而造成了当前的智能卡国际标准还不太完善的情况,据此,许多厂家又各自都对自己开发的COS作了一些扩充。就目前而言,还没有任何一家公司的CoS产品能形成一种工业标准。因此本章将主要结合现有的(指1994年以前)国际标准,重点讲述CO5的基本原理以及基本功能,在其中适当地列举它们在某些产品中的实现方式作为例子。
COs的主要功能是控制智能卡和外界的信息交换,管理智能卡内的存储器并在卡内部完成各种命令的处理。其中,与外界进行信息交换是coS最基本的要求。在交换过程中,COS所遵循的信息交换协议目前包括两类:异步字符传输的 T=0协议以及异步分组传输的T=l协议。这两种信息交换协议的具体内容和实现机制在ISO/IEC7816—3和ISO/IEC7816—3A3标准中作了规定;而COS所应完成的管理和控制的基中功能则是在ISO/IEC7816—4标准中作出规定的。在该国际标准中,还对智能卡的数据结构以及COS的基本命令集作出了较为详细的说明。至于ISO/IEC7816—1和2,则是对智能卡的物理参数、外形尺寸作了规定,它们与COS的关系不是很密切。
2 COS的体系结构
在这里需要提起注意的是,智能卡中的“文件”概念与我们通常所说的“文件”是有区别的。尽管智能卡中的文件内存储的也是数据单元或记录,但它们都是与智能卡的具体应用直接相关的。一般而言,一个具体的应用必然要对应于智能卡中的一个文件,因此,智能卡中的文件不存在通常所谓的文件共享的情况。而且,这种文件不仅在逻辑广必须是完整的,在物理组织上也都是连续的。此外,智能卡中的文件尽管也可以拥有文件名(FileN8me),但对文件的标识依靠的是与卡中文件—一对应的文件标识符(F3te ldentifier),而不是文件名。因为智能卡中的文件名是允许重复的,它在本质上只是文件的一种助记符,并不能完全代表莱个文件。
1.传送管理(Transmission Manaeer)
我们在前面提到过目前智能卡采用的信息传输协议一般是T=0协议和T=1协议,如果说这两类协议的COS在实现功能上有什么不同的话,主要就是在传送管理器的实现上有不同。不过,无论是采用T=0协议还是T=1协议,智能卡在信息交换时使用的都是异步通信模式;而且由于智能卡的数据端口只有一个,此信息交换也只能采用半双工的方式,即在任一时刻,数据端口上最多只能有一方(智能卡或者读写设备)在发送数据。 T=0、T=1协议的不同之处在于它们数据传输的单位和格式不一样,T=0协汉以单字节的字符为基本单位,T=1协议则以有一定长度的数据块为传输的基本单位。传送管理器在对命令进行接收的同时,也要对命令接收的正确性作出判断。这种判断只是针对在传输过程中可能产生的错误预言的,并不涉及命令的具体内容,因此通常是利用诸如奇偶校验位、校验和等手段来实现。对分组传输协议,则还可以通过判断分组长度的正确与否来实现。当发现命令接收有错后,不同的信息交换协议可能会有不同的处理方法:有的协议是立刻向读写设备报告,并且请求重发原数据;有的则只是简单地在响应命令上作一标记,本身不进行处理,留待它后面的功能模块作出反应。这些都是由交换协议本身所规定的。
智能卡的安全体系是智能卡的COs中一个极为重要的部分,它涉及到卡的鉴别与核实方式的选择,包括COS在对卡中文件进行访问时的权限控制机制,还关系列卡中信息的保密机制。可以认为,智能卡之所以能够迅速地发展并且流行起来.其中的一个重要的原因就在于它能够通过COS的安全体系给用户提供—个较高的安全性保证。安全体系在概念上包括三大部分:安全状态(Security Status),安全属性(Security Attributes)以及安全机制(Security Machanisms)。其中,安全状态是指智能卡在当前所处的一种状态,这种状态是在智能—卡进行完复位应答或者是在它处理完某命令之后得到的。事实上,我们完全可以认为智能卡在整个的工作过程中始终都是处在这样的、或是那样的一种状态之中,安全状态通常可以利用智能卡在当前已经满足的条件的集合来表示。安全属性实际上是定义了执行某个命令所需要的一些条件,只有智能卡满足了这些条件,该命令才是可以执行的。因此,如果将智能卡当前所处的安全状态与某个操作的安全属性相比较,那么根据比较的结果就可以很容易地判断出一个命令在当前状态下是否是允许执行的,从而达到了安全控制的目的。和安全状态与安全属性相联系的是安全机制。安全机制可以认为是安全状态实现转移所采用的转移方法和手段,通常包括:通行字鉴别,密码鉴别,数据鉴别及数据加密。一种安全状态经过上述的这些手段就可以转移到另一种状态,把这种状态与某个安全属性相比较,如果一致的话,就表明能够执行该属性对应的命令,这就是COS安全体系的基本工作原理。
鉴别则是通过智能卡和读写设备双方同时对任意一个相同的随机数进行某种相同的加密运算(目前常用 DES算法),然后判断双方运算结果的一致性来达到验证的日的的。
根据所鉴别的对象的不同,COS又把鉴别分为内部鉴别(Interna1 Authentication)和外部鉴别(External Authentication)两类。这里所说的“内部”、“外部”均以智能卡作为参照点,因此,内部鉴别就是读写设备对智能卡的合法性进行的验证;外部签别就是智能 F对读写设备的合法性进行的验证。至于它们的具体的实现方式.我们在第5章中已有详细论述,此处不再重复。
(2)密码管理:目前智能卡中常用的数据加密算法是DES算法。采用DES算法的原因是因为该算法已被证明是一个十分成功的加密算法,而且算法的运算复杂度相对而言也较小,比较适用于智能卡这样运算能力不是很强的情况。 DES算法的密码(或称密钥)长度是64位的。 COS把数据加密时要用到的密码组织在一起,以文件的形式储存起来,称为密码文件。最简单的密码文件就是长度为8个字节的记录的集合,其中的每个记录对应着一个DES密码;较为复杂的密码文件的记录中则可能还包含着该记录所对应的密码的各种属性和为了保证每个记录的完整性而附加的校验和信息,其结构如图6.37所示。
Key = DES(CTC, K(a))
3.应用管理器(Application Manager)
4.文件管理器(File Manager)
与安全一样,文件也是COs中的一个极为重要的概念。所谓文件,是指关于数据单元或卡中记录的有组织的集合。 COS通过给每种应用建立一个对应文件的方法来实现它对各个应用的存储及管理。因此,COS的应用文件中存储的都是与应用程序有关的备种数据或记录。此外,对某些智能卡的CoS,可能还包含有对应用文件进行控制的应用控制文件。在COS中,所有的文件都有一个唯一的文件标识符(File ldentifier),因此通过文件标识符就可以直接查找所需的文件。此外,每个文件还可以有一个文件名作为助记符,它与文件标识符的不同之处在于它是可以重复的。COS中的各文件在智能卡的个人化过程中由发行商(Issuer)根据卡的应用而创建,对卡的用户而言通常是不能对文件进行创建或删除的。但是用户可以根据情况对文件内容进行修改,可以对文件中的记录或数据单元进行增加、删除等操作。
(l)文件系统:COS的文件按照其所处的逻辑层次可以分为三类;主文件(MasterFile),专用文件(Dedicated File)以及基本文件(EIementary File)。其中,主文件对任何COS都是必不可少的,它是包含有文件控制信息及可分配存储区的唯一文件,其作用相当于是COS文件系统的根文件,处于COS文件系统的最高层;基本文件也是必不可少的一个部分,它是实际用来存储备应用的数据单元或记录的文件,处于文件系统的最底层,而专用文件是可选的,它存储的主要是文件的控制信息、文件的位置、大小等数据信息。我们可以用图6.38的树状结构来形象地描述一个COS的文件系统的基本结构。
        |                                   |                           |---------EF
        |                                    |-----------------DF--------EF
        |                            |-----------EF
采用鉴别寄存器方式时,通常是在内存RAM中设置一个8位(或者是16位)长的区域作为鉴别用寄存器。这里的鉴别是指对安全控制密码的鉴别。鉴别用寄存器所反映的是智能卡在当前所处的安全状态。采用这种方式时,智能卡的每个文件的文件头(或者是文件描述器)中通常都存储有该文件能够被访问的条件,——般是包括读、写两个条件r分别用Cr、Cu表示),这就构成了该文件的安全属性。而用户通过向智能卡输入安全密码.就可以改变卡的安全状态,这一过程我们j至常称为出示,这就是鉴别寄存器为式的安全机制。把上面的二方面结合起来,就能够对卡中文件的读写权限加以控制了。具体的操作机制我们以 PCOS为例加以描述。
首先,PBOS中的鉴别寄存器是8位字长的,这 s位dI的假;位分别与PC()3存储器中保密宇区(参见园6.34)内的7个安全密码的序号一一对应。寄存器中每——位的初始值都被置为“0”。如果用户向智能卡出示了某一个安全密妈,并且被F判断为正确的话,系统就在鉴别寄存器的相应位上写入“1”。例如,如果处于保密宇区中的第2个安全密码被用户正确出示的话,PCOS就在寄存器的第2位上写“1”。同时,文件描述器中的读、写条件Cr、Cu保存的都是在0和7之间的一个数,它的值对应于该文件进行读(或写)操作时所需要出示的密码在保密宇区小的序号。在对某个文件进行读(或写)操作之前,系统首先判断在鉴别寄存器巾对应的第Cr(或Cu)位是否已被置为“1”(如果Cr等于0,就表示该文件可以被用户随意读取;对于Cu也是一样),只有当该位为“1”时,才表示读(或写)权限已经得到满足.才能对该文件进行读(或写)操作。这也就是说,如果用户想要对一个文件进行操作的话,就必须要首先出示对应于该文件的安全属性为正确的安全密码。系统据此就达到了对文件的访问进行安全控制的目的。
与鉴别寄存器方式完全不一样,状态机方式更加明显地表示出扩安全状态、安全属性以及安全机制的概念以及它们之间的关系(关于状态机的知识不属于本书的范畴,有兴趣的读者请自行查阅有关资料)。以5TARCOS为例,它采用的是‘—种确定状态机的机制,该机制通过系统内的应用控制文件(Applicatlon ControIFile,ACF)而得以实现。 ACF文件的格式如图6.39所示,已是一个线性变长结构的文件,其rh记录 01包括了该ACP所控制的应用可以允许的所有命令的指令码(INS);其余的记录分别与记录 01中的指令码一一对应,其中存储的都是对府命令的变体(Varient)纪录。所谓变体记录指的是这样的一些记录。记录中存储的是控制信息、初始状态、可能的下一状态以及某些附加的指令信富的组台,利用 ACF 中的这些变体记录就可以形成状态转移图。在变体记录中,控制信息部分是必不可少的。不同的变体记录主要在两个方面有区别:一是命令所允许的状态不同t二是以CLA宇节开始的指令信息部分不相同。这主要是由命令要操作的应用对象的不同而决定的。
利用 ACF,COS系统就可以实现对文件访问的安全控制了。当系统接收到一个应用进行操作的一条命令后,首先检验其指令码是否在相应的ACF文件的记录01中。如果不在其中,系统就认为该命令是错误的。在找到了对应的指令码后,系统把命令的其余部分与该命令对应的备变体记录中的指令信息按照该变体记录的控制信息的要求进行比较,如果比较结果一致,那么再查验变体记录中的初始状态信息。若所有这些检测都顺利通过,那么系统就进入对应变体记录中指明的下一状态;否则,继续查找下一个变体记录直到发现相应变体或是查完该命令对应的所有变体记录为止。如果没有找到相应的变体记录,说明该命令是非法的;否则就进入下一步对命令的处理,即由 COS调用实际的处理过程执行对命令的处理。当且仅当处理过程正常结束的时候,系统才进入一个新的状态,并开始等待对下一条命令的接收。
(转自:≡中国电子技术信息网≡ 网址


智能卡的名称来源于英文名词“Smart card”,又称集成电路卡,即 IC卡(Integrated Circuitcard)。它将一个集成电路芯片镶嵌于塑料基片中,封装成卡的形式,其外形与覆盖磁条的磁卡相似。
IC卡的概念是7O年代初提出来的,法国布尔(BULL)公司于1976年首先创造出 IC卡产品,并将这项技术应用到金融、交通、医疗、身份证明等多个行业,它将徽电子技术和计算机技术结合在一起,提高了人们生活和工作的现代化程度。
1.存储器卡 卡中的集成电路为EEPROM(可用电擦除的可编程只读存储器
2.逻辑加密卡 卡中的集成电路具有加密逻辑和ZEPROM。
3.CPU卡 卡中的集成电路包括中央处理器CPU、EEPROM、随机存储器RAM以及固化在只读存储器ROM中的片内操作系统COS(ChiPOperatingSystem)。
金融卡又有信用卡(credtt card)和现金卡(debit card)等。信用卡主要由银行发行和管理,持卡人用它作为消费时的支付工具,可以使用预先设定的透支限额资金。现金卡可用作电子存折和电子钱包,不允许透支。
为了使用卡片,还需要有与IC卡配合工作的接口设备IFD(InterFace Device),或称为读写设备。IFD可以是一个由微处理器、键盘、显示器与I/O接口组成的独立设备,该接口设备通过IC卡上的8个触点向IC卡提供电源井与IC卡相互交换信息。IFD也可以是一个简单的接口电路,IC卡通过该电路与通用微机相连接。无论是磁卡或IC卡,在卡上能存储的信息总是有限的,因此大部分信息需要存放在接口设备或计算机中。当用信用卡购物时,如在允许透支范围内,则可以先取走商品,事后再结算;如需一笔大款,则需经银行确认,授权于商店后,才能取走商品。由于银行、发放信用卡的公司以及商店不在同一处,因此需要经过通信线路和计算机(主机)联系才能实现上述过程。
1.2.1 IC卡提供的信息
1.印在卡上的可供人阅读的信息 用以标识卡发行人的标志、使用期限、客户姓名、帐号和签名等,这些信息是卡能作为金融交易中的支付工具的基础。
2.机器可读数据 卡上的凸出字符用于压印帐单,以便向售货商和客户提供交易凭证。卡上还可提供金融交易的帐目。
自动柜员机是放在银行或商店大堂中供客户自动提款的机器(有的 ATM还有自动存款功能)。执行从ATM提取现金的操作仅需十几秒钟,总共只需要作出4个输入动作:
当 ATM判别没有问题时,自动输出卡和现金,并打印凭证。由此可见,ATM是一种操作方便的信息处理系统,可以24小时提供服务。
1.2.3 IC卡存储区的分配和功能简介
1.公开的(不保密的)存储区 内含公用信息,诸如发行标识符,持卡人的帐号等。
2.外部不可读的存储区 存储的内容是供内部决策用的,如PIN值,该值是在卡片发行时进行个人化处理写入的,用户在输入正确的PIN值后,允许输入新PIN值进行修改,但在任何情况下,都不允许将存储在卡中的PIN值向外界传送。在本存储区内还可能存放密钥。
3.保密存储区 内含帐面余额、允许卡使用的服务类型及限额等。当持卡人输入正确的PIN值后,允许读取本存储区数据,并根据应用情况写入正确数据(如修改余额)。
4.记录区 内含每次交易细节,称为日志,可供查询。
1.交易数据 内含每次交易记录,一般于每天晚上将当天交易细节汇总后传送到开户银行或发卡银行,供转帐和清算之用。银行应保证及时将应付款存入售货商帐户。
3.保密数据 密钥和授权电话号码即属于保密数据,密钥用以生成校验码以防交易日志被修改。至于授权电话,在售货商希望成交某些超额交易时,用它接通用户银行,经银行授权后方可受理,如果电话通信线路很忙,那么等待授权的时间可能很长,甚至能让客户觉得无法容忍,这就会影响到金融卡的推广应用。较先进的系统应靠计算机网络和通信线路来完成授权功能。
·安全可靠:每次交易正确无误,操作错误后的重新启动方便可靠,卡片的丢失、被窃和 PIN值的更换等容易处理。
除了满足商店和用户的要求以外,应做好有关方面(银行、商店、用户)之间的信息交换工作,以及用户忘了 PIN后的处理工作等。
1.信用卡 卡中预先建立允许透支的限额,即预先设置好可借用的资金额度,承谱到期归还并支讨利息的责仟。根据持卡人信用程度的不同,有两种信用卡:金卡和普j园长。前者的透支限额高。
3.ATM卡 只能在ATM中使用的现金卡或信用卡。
4.预付卡 按卡面价值购买,先购买后使用,例如电话和公共系统用的预付卡,电表预付卡等。
1.智能卡和接口设备之间的信息流j恿 这些流通的信息可以被截取分析,从而可被复制或插入假信号。
3.在交易中司更换智能卡 在授权过程个使用的是合法的智能卡,而在交易数据写入之前更换成另一张卡,因此将交易数据写入替代卡中。
4.修改信用卡中控制余额更新的日期 信用卡使用时需要输入当天日期,以供卡判断是否是当天第一次使用,即是否应将有效余额项更新为最高授权余额(也即是前面讲到的,允许一天内支取的最大金额),如果修改控制余额更新的日期(郧上次使用的日期),并将它提前,则输入当天日期后,接口设备会误认为是当天第一次取款,于是将有效余额更新为最高授权余额,因此利用窃来的卡可取定最高授权的金额,其危害性还在于(在银行提出新的黑名单之前)可重复多次作弊。
5.商店雇员的作弊行为 接口设备写入卡中的数据不正确,或雇员私下将一笔交易写成两笔交易,因此接口设备不允许被借用、私自拆卸或改装。
(1)信息验证 防止信息被篡改,保护信息的完整性,要求在接收时能发现被策改的数据,例如可采用一定的算法产生附加的校验炳,在接收点进行检验。
(3)身份认证:用 password或个人身份号PIN进行认证.更可靠的是利用生物特征。
1.呆帐 持卡人到时不付帐。
2.作弊 是由于犯罪行为引起的,因此在塑料卡亡采取厂一些防范措施。例如VISA卡采取了以下措施:正面有全息飞鸽图形;精细的底版印刷;非凸形的标识号,卡片上有签字条,当签字被更改时,签字条立即显示出 VOID(作废)。
识别卡是一种可识别其发行者和待有者的卡。金长支付业务中用得最多的是信用卡,它是一种识别卡。识别卡分磁卡和 IC卡两类。
1.物理特性 包括卡的材料、构造、特性、标称尺寸等均应符合国际标准ISO7816:1985。
2.凸印 卡正面显著地凸起的字符称为凸印,用于数据传送,这种传送可以通过压印机,也可以用目视或机器阅读。凸印字符包含标识号,持卡人的姓名和地址。常用的ID—l型卡上凸印字符的位置应符合国际标准SO7SII—3:1985的规定。
凸印字符及其字体的选择应符合ISO tO73—I和 ISO lO73—2和 ISO7811—l附录B、附录C描述的7B字体的规定,凸印字符的字符间距、高度等符合国际标准 ISO7811—1:1985的规定。凸印字符的印刷规范符合ISO1831:1980的规定。
3.磁条 磁条上磁性材料的物理特性和性能特性、编码技术和编码字符集有相应的国际标准ISO7811—2:1985。磁条上:共有三个磁道,第一、二磁道为只读磁道,第三磁道为读写磁道,分别有国际标准ISO7811—4:1985和 ISO7811—5:1985。
1.4.2 IC卡(接触型)的国际标准
1.物理特性 符合ISO7816:1987中规定的各类识别卡的物理特性和ISO7813中规定的金融交易卡的全部尺寸要求,此外还应符合国际标准ISO7816—1:1987规定的附加特性、机械强度和静电测试方法。
应符合国际标准ISO 7816—2:1988中的规定。
IC卡与接口设备之间电源及信息交换应符合 ISO/IEC7816—3:1989的规定。
5.应用标识符的编号系统和注册过程 应符合国际标准ISO/IEC7816—5:1994中的规定。
(转自:≡中国电子技术信息网≡ 网址


  • 2007年11月17日 12:20
  • 1.54MB
  • 下载

windows PC/SC 常用Scard前缀函数说明

Windows系统提供了大量的API来方便的进行智能卡应用程序的开发,通过它们我们可以直接控制智能卡读卡器对智能卡进行操作,也可以与智能卡建立直接的虚拟连接而不用考虑智能卡读卡器。 智能卡应用程序开...



windows PC/SC 常用Scard前缀函数说明



通常是: scard0:指系统内部存储 scard1:指外插的sd卡 也有特例。。 分别获取路径的方法: package com.main; import java.lang.reflect.Me...


用gensim函数库训练Word2Vec模型有很多配置参数。这里对gensim文档的Word2Vec函数的参数说明进行翻译,以便不时之需。 class gensim.models.word2vec....
  • szlcw1
  • szlcw1
  • 2016年10月07日 19:26
  • 8041


本系列文章我将和大家一起来发掘cocos2d-x中所使用到的设计模式,同样的,这些模式在cocos2d-iphone中也可以找到其身影。 声明:这里发掘模式只是我的个人爱好,通过这个过程,我希望...
  • w00w12l
  • w00w12l
  • 2013年12月09日 10:32
  • 6756


【前言】 假如大家已经弄懂了b树及b+树那么恭喜你们了,因为我觉得,b树及b+树是文件系统尤其是数据库优化的关键。 这里预告一下,下一篇课题(也不能说课题,只能用“业余研究题目”这种称呼)是R树,...
  • cdnight
  • cdnight
  • 2013年09月06日 21:57
  • 5329

Pro Android学习笔记(一一六):Location(2):LocationManager的位置获取

文章转载只能用于非商业性质,且不能带有虚拟货币、积分、注册等附加条件。转载须注明出处以及作者@恺风Wei-傻瓜与非傻瓜。 Loca...


1、损失函数         损失函数在统计学中是一种衡量损失和误差程度的函数,它一般包括损失项(loss term)和正则项(regularization term)。     损失项     ...