http://blog.csdn.net/aaaaatiger/category/323085.aspxVerilogHDL,VHDL,SystemC,CPLD,FPGA,Cadence,OR1200,Modelsim,plizh-CNSun, 20 Apr 2008 01:50:40 GMT60aaaaatigerhttp://blog.csdn.net/aaaaatiger/archive/2007/10/22/1837934.aspxMon, 22 Oct 2007 20:11:00 GMThttp://blog.csdn.net/aaaaatiger/archive/2007/10/22/1837934.aspxhttp://blog.csdn.net/aaaaatiger/comments/1837934.aspxhttp://blog.csdn.net/aaaaatiger/archive/2007/10/22/1837934.aspx#Feedback0http://blog.csdn.net/aaaaatiger/comments/commentRss/1837934.aspxhttp://tb.blog.csdn.net/TrackBack.aspx?PostId=1837934<img src ="http://blog.csdn.net/aaaaatiger/aggbug/1837934.aspx" width = "1" height = "1" />aaaaatigerhttp://blog.csdn.net/aaaaatiger/archive/2007/09/05/1773783.aspxWed, 05 Sep 2007 20:45:00 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