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s5pv210 cpu硬件资源

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先来看一下210cpu的硬件资源框架


S5PV210 主要特色包括


     ARM CortexTM-A8 based CPU Subsystem with NEON 


         32/ 32 KB I/D Cache, 512 KB L2 Cache 


         Operating frequency up to 800 MHz at 1.1V, 1 GHz at 1.2V 


     64-bit Multi-layer bus architecture 


         MSYS domain for ARM CortexTM-A8, 3D engine, Multi Format Codec and Interrupt Controller 


     Operating frequency up to 200 MHz at 1.1V 


         DSYS domain mainly for Display IPs (such as LCD controller, Camera interface, and TVout), and MDMA 


     Operating frequency up to 166 MHz at 1.1V 


         PSYS domain mainly for other system component such as system peripherals, external memory interface, 
         peri DMAs, connectivity IPs, and Audio interfaces. 


     Operating frequency up to 133 MHz at 1.1V 


         Audio domain for low power audio play 


     Advanced power management for mobile applications 


     64 KB ROM for secure booting and 128 KB RAM for security function 


     8-bit ITU 601/656 Camera Interface supports horizontal size up to 4224 pixels for scaled and 8192 pixels for 
    un-scaled resolution 


     Multi Format Codec provides encoding and decoding of MPEG-4/H.263/H.264 up to 1080p@30fps and 
    decoding of MPEG-2/VC1/Divx video up to 1080p@30 fps 


     JPEG codec supports up to 80 Mpixels/s 


     3D Graphics Acceleration with Programmable Shader up to 20M triangles/s and 1000 Mpixels/s 


     2D Graphics Acceleration up to 160Mpixels/s 


     1/ 2/ 4/ 8 bpp Palletized or 8/ 16/ 24 bpp Non-Palletized Color TFT recommend up to XGA resolution 


     TV-out and HDMI interface support for NTSC and PAL mode with image enhancer 


     MIPI-DSI and MIPI-CSI interface support 


     One AC-97 audio codec interface and 3-channel PCM serial audio interface 


     Three 24-bit I2S interface support 


     One TX only S/PDIF interface support for digital audio 


     Three I2C interface support 


     Two SPI support 


     Four UART supports three Mbps ports for Bluetooth 2.0 


     On-chip USB 2.0 OTG supports high-speed (480 Mbps, on-chip transceiver) 


     On-chip USB 2.0 Host support 


     Asynchronous Modem Interface support 


     Four SD/ SDIO/ HS-MMC interface support 


     ATA/ ATAPI-6 standard interface support 


24-channel DMA controller (8 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA) 


     Supports 14x8 key matrix 


     10-channel 12-bit multiplexed ADC 


     Configurable GPIOs 


     Real time clock, PLL, timer with PWM and watch dog timer 


     System timer support for accurate tick time in power down mode (except sleep mode) 


     Memory Subsystem 


         Asynchronous SRAM/ ROM/ NOR Interface with x8 or x16 data bus 


         NAND Interface with x8 data bus 


         Muxed/ Demuxed OneNAND Interface with x16 data bus 


         LPDDR1 Interface with x16 or x32 data bus (266~400 Mbps/ pin DDR) 


         DDR2 interface with x16 or x32 data bus (400 Mbps/ pin DDR) 


         LPDDR2 interface (400 Mbps/ pin DDR) 


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