翻译2440 CLOCK & POWER MANAGEMENT

7 CLOCK & POWER MANAGEMENT

 

OVERVIEW

The Clock & Power management block consists of three parts: Clock control, USB control, and Power control.

时钟和电源管理模块由三部分组成：时钟控制，USB控制和电源控制。

 

The Clock control logic in S3C2440A can generate the required clock signals including FCLK for CPU, HCLK for the AHB bus peripherals, and PCLK for the APB bus peripherals. The S3C2440A has two Phase Locked Loops (PLLs):one for FCLK, HCLK, and PCLK, and the other dedicated for USB block (48Mhz). The clock control logic can make slow clocks without PLL and connect/disconnect the clock to each peripheral block by software, which will reduce the power consumption.

S3C2440A中的时钟控制逻辑可以产生CPU的时钟FCLK，AHB (Advanced High performance Bus)系统总线外设的HCLK以及APB (Advanced Peripheral Bus)外围总线的PCLK。S3C2440A有两个锁相环（PLL）一个用于FCLK，HCLK以及PCLK，另外一个用于USB模块（48Mhz）。时钟控制逻辑可以控制输出慢时钟，可以不使用PLL ，可以用软件连接/断开每个外部模块的的时钟，这样可以降低功耗。

 

For the power control logic, the S3C2440A has various power management schemes to keep optimal power consumption for a given task. The power management block in the S3C2440A can activate four modes: NORMAL mode, SLOW mode, IDLE mode, and SLEEP mode.

S3C2440A有多方面的电源管理配置根据所给任务以获得最理想的电源功耗。S3C2440A的电源管理模块可以激活四种模式：正常模式，慢速模式，空闲模式以及休眠模式。（附：我没有理会For the power control logic这句，因为我不知道它和段中要表达的是什么什么，嘿嘿，各位觉得怎么翻译才好，请留言指点！）

 

NORMAL mode: The block supplies clocks to CPU as well as all peripherals in the S3C2440A. In this mode, the power consumption will be maximized when all peripherals are turned on. It allows the user to control the operation of peripherals by software. For example, if a timer is not needed, the user can disconnect the clock(CLKCON register) to the timer to reduce power consumption.

正常模式：时钟提供给CPU以及所有S3C2440A外设。这种模式下，所有外设打开，功耗是最大的。此时，允许用户用软件控制外设，比如，如果不需要定时器了，用户可以断开它的时钟（通过CLKCON 寄存器设置）以降低电源功耗。

 

SLOW mode: Non-PLL mode. Unlike the Normal mode, the Slow mode uses an external clock (XTIpll or EXTCLK)directly as FCLK in the S3C2440A without PLL. In this mode, the power consumption depends on the frequency of the external clock only. The power consumption due to PLL is excluded.

慢速模式：无锁相环模式，和正常模式不同，慢速模式是直接使用外部时钟给FCLK。在这种模式下，电源功耗决只是决定于外部时钟频率。电源功耗降低源于没有使用PLL。

 

IDLE mode: The block disconnects clocks (FCLK) only to the CPU core while it supplies clocks to all other peripherals. The IDLE mode results in reduced power consumption due to CPU core. Any interrupt request to CPU can be woken up from the Idle mode.

空闲模式：断开给CPU core的时钟（FCLK），同时供时钟给所有外设。空闲模式能减小功耗是因为少了CPU core损耗。任何中断产生都可以使CPU从空闲模式唤醒。（这里我不明白，这个CPU core 都不工作了，咋还能唤醒呢？难道是因为中断属于外设总线的一部分？）

 

SLEEP mode: The block disconnects the internal power. So, there occurs no power consumption due to CPU and the internal logic except the wake-up logic in this mode. Activating the SLEEP mode requires two independent power sources. One of the two power sources supplies the power for the wake-up logic. The other one supplies other internal logics including CPU, and should be controlled for power on/off. In the SLEEP mode, the second power supply source for the CPU and internal logics will be turned off. The wakeup from SLEEP mode can be issued by the EINT[15:0] or by RTC alarm interrupt.

 

休眠模式：断开内部电源，所以功耗下降源于CPU和内部电源逻辑，唤醒逻辑为断电。激活休眠模式需要两个独立的带电源，一个是供给唤醒逻辑的电源，一个是供给其他内部逻辑的电源，包括CPU，并且应该控制电源开/关。在休眠模式中，第二个供给CPU和内部逻辑的电源要关闭。从休眠模式唤醒需要外部中断EINT[15:0]或者RTC报警中断产生。

太长，等下我上传到资源供下载。有什么错误请回复指出哦。我也没有时间再审核。