头文件:
#ifndef AT91_PWM_H
#define AT91_PWM_H
#define PWMC_BASE 0xfffb8000
/**************** pwm模式寄存器偏移0x00 *****************/
#define PWM_MR_OFF 0x00000000 ///< PWM Mode Register offset.
#define PWM_MR (*((volatile unsigned long *)(PWMC_BASE + PWM_MR_OFF))) ///< PWM Mode Register.
#define PWM_MR_DIVA_MASK 0x000000FF ///< PWM Mode Divide factor A Mask.
#define PWM_MR_DIVA_SHIFT 0 ///< PWM Mode Divide factor A LSB.
#define PWM_MR_DIVB_MASK 0x00FF0000 ///< PWM Mode Divide factor B Mask.
#define PWM_MR_DIVB_SHIFT 16 ///< PWM Mode Divide factor B LSB.
#define PWM_MR_PREA_MASK 0x00000F00 ///< PWM Mode prescaler A Mask.
#define PWM_MR_PREA_SHIFT 8 ///< PWM Mode prescaler A LSB.
#define PWM_MR_PREB_MASK 0x0F000000 ///< PWM Mode prescaler B Mask.
#define PWM_MR_PREB_SHIFT 24 ///< PWM Mode prescaler B LSB.
#define PWM_MR_PRE_MCK 0 ///< PWM Mode prescaler set to MCK.
#define PWM_MR_PRE_MCK_DIV2 1 ///< PWM Mode prescaler set to MCK/2.
#define PWM_MR_PRE_MCK_DIV4 2 ///< PWM Mode prescaler set to MCK/4.
#define PWM_MR_PRE_MCK_DIV8 3 ///< PWM Mode prescaler set to MCK/8.
#define PWM_MR_PRE_MCK_DIV16 4 ///< PWM Mode prescaler set to MCK/16.
#define PWM_MR_PRE_MCK_DIV32 5 ///< PWM Mode prescaler set to MCK/32.
#define PWM_MR_PRE_MCK_DIV64 6 ///< PWM Mode prescaler set to MCK/64.
#define PWM_MR_PRE_MCK_DIV128 7 ///< PWM Mode prescaler set to MCK/128.
#define PWM_MR_PRE_MCK_DIV256 8 ///< PWM Mode prescaler set to MCK/256.
#define PWM_MR_PRE_MCK_DIV512 9 ///< PWM Mode prescaler set to MCK/512.
#define PWM_MR_PRE_MCK_DIV1024 10 ///< PWM Mode prescaler set to MCK/1024.
#define PWM_CHID_MASK 0x0000000F
#define PWM_CHID0 0
#define PWM_CHID1 1
#define PWM_CHID2 2
#define PWM_CHID3 3
/*********************** pwm使能寄存器偏移0x04 *****************/
#define PWM_ENA_OFF 0x00000004 ///< PWM Enable Register offset.
#define PWM_ENA (*((volatile unsigned long *)(PWMC_BASE + PWM_ENA_OFF))) ///< PWM Enable Register.
/*********************** pwm去使能寄存器0x08 *****************/
#define PWM_DIS_OFF 0x00000008 ///< PWM Disable Register offset.
#define PWM_DIS (*((volatile unsigned long *)(PWMC_BASE + PWM_DIS_OFF))) ///< PWM Disable Register.
/********************* pwm状态寄存器0x0C *****************/
#define PWM_SR_OFF 0x0000000C ///< PWM Status Register offset.
#define PWM_SR (*((volatile unsigned long *)(PWMC_BASE + PWM_SR_OFF))) ///< PWM Status Register.
/********************** pwm中断使能寄存器0x10 *****************/
#define PWM_IER_OFF 0x00000010 ///< PWM Interrupt Enable Register offset.
#define PWM_IER (*((volatile unsigned long *)(PWMC_BASE + PWM_IER_OFF))) ///< PWM Interrupt Enable Register.
/********************** pwm中断去使能寄存器0x14 *****************/
#define PWM_IDR_OFF 0x00000014 ///< PWM Interrupt Disable Register offset.
#define PWM_IDR (*((volatile unsigned long *)(PWMC_BASE + PWM_IDR_OFF))) ///< PWM Interrupt Disable Register.
/********************** pwm中断掩码寄存器0x18 *****************/
#define PWM_IMR_OFF 0x00000018 ///< PWM Interrupt Mask Register offset.
#define PWM_IMR (*((volatile unsigned long *)(PWMC_BASE + PWM_IMR_OFF))) ///< PWM Interrupt Mask Register.
/********************** pwm中断状态寄存器0x1c *****************/
#define PWM_ISR_OFF 0x0000001C ///< PWM Interrupt Status Register offset.
#define PWM_ISR (*((volatile unsigned long *)(PWMC_BASE + PWM_ISR_OFF))) ///< PWM Interrupt Status Register.
/********************** pwm通道模式寄存器 0x200+ch_num*0x20+0x00 *****************/
#define PWM_CH0_OFF 0x00000200 ///< PWM Channel 0 registers offset.
#define PWM_CH1_OFF 0x00000220 ///< PWM Channel 1 registers offset.
#define PWM_CH2_OFF 0x00000240 ///< PWM Channel 2 registers offset.
#define PWM_CH3_OFF 0x00000260 ///< PWM Channel 3 registers offset.
#define PWM_CMR_OFF 0x00000000 ///< PWM Channel Mode Register offset.
#define PWM_CMR0 (*((volatile unsigned long *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH0_OFF))) ///< PWM Channel 0 Mode Register.
#define PWM_CMR1 (*((volatile unsigned long *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH1_OFF))) ///< PWM Channel 1 Mode Register.
#define PWM_CMR2 (*((volatile unsigned long *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH2_OFF))) ///< PWM Channel 2 Mode Register.
#define PWM_CMR3 (*((volatile unsigned long *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH3_OFF))) ///< PWM Channel 3 Mode Register.
#define PWM_CPRE_MCK_MASK 0x0000000F ///< PWM Mode prescaler mask.
#define PWM_CPRE_MCK 0 ///< PWM Mode prescaler set to MCK.
#define PWM_CPRE_MCK_DIV2 1 ///< PWM Mode prescaler set to MCK/2.
#define PWM_CPRE_MCK_DIV4 2 ///< PWM Mode prescaler set to MCK/4.
#define PWM_CPRE_MCK_DIV8 3 ///< PWM Mode prescaler set to MCK/8.
#define PWM_CPRE_MCK_DIV16 4 ///< PWM Mode prescaler set to MCK/16.
#define PWM_CPRE_MCK_DIV32 5 ///< PWM Mode prescaler s