linux USB HOST之EHCI和OHCI

最新推荐文章于 2023-09-05 20:42:14 发布
VIP文章 最新推荐文章于 2023-09-05 20:42:14 发布
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分类专栏： USB
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1. 主机控制器(Host Controller)

      • UHCI: Universal Host Controller Interface (通用主机控制接口, USB1.0/1.1)
      • OHCI: Open Host Controller Interface (开放主机控制接口,USB1.0/1.1)
      • EHCI: Enhanced Host Controller Interface (用于USB2.0高速设备的“增强主机控制接口”)    

     USB的拓扑结构决定了主机控制器就是最高统帅，没有主机控制器的要求设备永远不能主动发数据。所以主机控制器在USB的世界里扮演着重要的角色，它是幕后操纵者。

     比如说Host发送Setup包获取设备描述符是怎么发出去的?

    这个过程包含很多信息，比

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Enhanced Host Controller Interface Specification for Universal Serial Bus<br><br>1. INTRODUCTION...............................................................................................1 <br>1.1 EHCI Product Compliance.................................................................................................................2 <br>1.2 Architectural Overview.......................................................................................................................2 <br>1.2.1 Interface Architecture....................................................................................................................4 <br>1.2.2 EHCI Schedule Data Structures.....................................................................................................5 <br>1.2.3 Root Hub Emulation......................................................................................................................5 <br>2. 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Serial Bus Release Number Register.............................................................................9 <br>2.1.5 Frame Length Adjustment Register (FLADJ)..............................................................................10 <br>2.1.6 Port Wake Capability Register (PORTWAKECAP)...................................................................11 <br>2.1.7 USBLEGSUP ? USB Legacy Support Extended Capability.....................................................11 <br>2.1.8 USBLEGCTLSTS ? USB Legacy Support Control/Status........................................................12 <br>2.2 Host Controller Capability Registers...............................................................................................13 <br>2.2.1 CAPLENGTH ? Capability Registers Length...........................................................................13 <br>2.2.2 HCIVERSION ? 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USB Interrupt Enable Register..............................................................................22 <br>2.3.4 FRINDEX ? Frame Index Register............................................................................................23 <br>2.3.5 CTRLDSSEGMENT ? Control Data Structure Segment Register............................................24 <br>2.3.6 PERIODICLISTBASE ? Periodic Frame List Base Address Register......................................24 <br>2.3.7 ASYNCLISTADDR ? Current Asynchronous List Address Register.......................................25 <br>2.3.8 CONFIGFLAG ? Configure Flag Register................................................................................25 <br>2.3.9 PORTSC ? Port Status and Control Register.............................................................................26 <br>3. DATA STRUCTURES.....................................................................................31 <br>3.1 Periodic Frame List...........................................................................................................................31 <br>3.2 Asynchronous List Queue Head Pointer..........................................................................................32 <br>3.3 Isochronous (High-Speed) Transfer Descriptor (iTD)....................................................................33 <br>USB 2.0 i <br><br>EHCI Revision 1.0 3/12/2002 <br>3.3.1 Next Link Pointer.........................................................................................................................33 <br>3.3.2 iTD Transaction Status and Control List......................................................................................34 <br>3.3.3 iTD Buffer Page Pointer List (Plus).............................................................................................35 <br>3.4 Split Transaction Isochronous Transfer Descriptor (siTD)...........................................................36 <br>3.4.1 Next Link Pointer.........................................................................................................................37 <br>3.4.2 siTD Endpoint Capabilities/Characteristics.................................................................................37 <br>3.4.3 siTD Transfer State......................................................................................................................38 <br>3.4.4 siTD Buffer Pointer List (plus)....................................................................................................39 <br>3.4.5 siTD Back Link Pointer...............................................................................................................40 <br>3.5 Queue Element Transfer Descriptor (qTD).....................................................................................40 <br>3.5.1 Next qTD Pointer.........................................................................................................................41 <br>3.5.2 Alternate Next qTD Pointer.........................................................................................................41 <br>3.5.3 qTD Token...................................................................................................................................42 <br>3.5.4 qTD Buffer Page Pointer List......................................................................................................45 <br>3.6 Queue Head........................................................................................................................................46 <br>3.6.1 Queue Head Horizontal Link Pointer...........................................................................................46 <br>3.6.2 Endpoint Capabilities/Characteristics..........................................................................................47 <br>3.6.3 Transfer Overlay..........................................................................................................................49 <br>3.7 Periodic Frame Span Traversal Node (FSTN)................................................................................51 <br>3.7.1 FSTN Normal Path Pointer..........................................................................................................51 <br>3.7.2 FSTN Back Path Link Pointer......................................................................................................52 <br>4. OPERATIONAL MODEL................................................................................53 <br>4.1 Host Controller Initialization............................................................................................................53 <br>4.2 Port Routing and Control..................................................................................................................54 <br>4.2.1 Port Routing Control via EHCI Configured (CF) Bit..................................................................55 <br>4.2.2 Port Routing Control via PortOwner and Disconnect Event.......................................................56 <br>4.2.3 Example Port Routing State Machine..........................................................................................57 <br>4.2.4 Port Power....................................................................................................................................57 <br>4.2.5 Port Reporting Over-Current........................................................................................................58 <br>4.3 Suspend/Resume................................................................................................................................59 <br>4.3.1 Port Suspend/Resume..................................................................................................................59 <br>4.4 Schedule Traversal Rules..................................................................................................................61 <br>4.4.1 Example - Preserving Micro-Frame Integrity..............................................................................62 <br>4.5 Periodic Schedule Frame Boundaries vs Bus Frame Boundaries..................................................64 <br>4.6 Periodic Schedule...............................................................................................................................66 <br>4.7 Managing Isochronous Transfers Using iTDs.................................................................................67 <br>4.7.1 Host Controller Operational Model for iTDs...............................................................................67 <br>4.7.2 Software Operational Model for iTDs.........................................................................................69 <br>4.8 Asynchronous Schedule.....................................................................................................................71 <br>4.8.1 Adding Queue Heads to Asynchronous Schedule........................................................................71 <br>4.8.2 Removing Queue Heads from Asynchronous Schedule..............................................................72 <br>4.8.3 Empty Asynchronous Schedule Detection...................................................................................74 <br>ii USB 2.0 <br><br>EHCI Revision 1.0 3/12/2002 <br>4.8.4 Restarting Asynchronous Schedule Before EOF.........................................................................74 <br>4.8.5 Asynchronous Schedule Traversal : Start Event..........................................................................76 <br>4.8.6 Reclamation Status Bit (USBSTS Register)................................................................................77 <br>4.9 Operational Model for Nak Counter................................................................................................77 <br>4.9.1 Nak Count Reload Control...........................................................................................................78 <br>4.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads....................................................79 <br>4.10.1 Fetch Queue Head........................................................................................................................80 <br>4.10.2 Advance Queue............................................................................................................................81 <br>4.10.3 Execute Transaction.....................................................................................................................81 <br>4.10.4 Write Back qTD...........................................................................................................................86 <br>4.10.5 Follow Queue Head Horizontal Pointer.......................................................................................86 <br>4.10.6 Buffer Pointer List Use for Data Streaming with qTDs...............................................................86 <br>4.10.7 Adding Interrupt Queue Heads to the Periodic Schedule.............................................................88 <br>4.10.8 Managing Transfer Complete Interrupts from Queue Heads.......................................................88 <br>4.11 Ping Control.......................................................................................................................................88 <br>4.12 Split Transactions..............................................................................................................................89 <br>4.12.1 Split Transactions for Asynchronous Transfers...........................................................................90 <br>4.12.2 Split Transaction Interrupt...........................................................................................................92 <br>4.12.3 Split Transaction Isochronous....................................................................................................103 <br>4.13 Host Controller Pause......................................................................................................................114 <br>4.14 Port Test Modes...............................................................................................................................114 <br>4.15 Interrupts..........................................................................................................................................115 <br>4.15.1 Transfer/Transaction Based Interrupts.......................................................................................115 <br>4.15.2 Host Controller Event Interrupts................................................................................................117 <br>5. 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