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RSS订阅转载 vmm debug problem
Here is a reference of compile script and filelist, the DVE tbug is ok, please have a try. //---------------------test.files----------------------------------------AxiMaster_rvm.pkgAhbSlave
2012-01-29 18:24:02
2696
转载 How to covert AHB BUS monitor VIP to AHB Master Port monitor
Below is an example on how to covert the AHB Bus monitor to a Port Monitor for Master: Step 1: in the TBTop, do as below(wire-connection): //***************************************************
2012-01-29 18:12:39
2692
转载 How to generate response for AHB Slave VIP
You can create a “ahbSlaveResponser.sv” that extends from vmm_xactor, and the responses are “transfer” level based, that is, if a burst read/write have 4 transfers, the Slave VIP will send 4 objects t
2012-01-29 18:03:59
2591
转载 how to generate AXI VIP built-in coverage
There is a built-in AXI VIP example that can show you how to generate AXI VIP built-in coverage, it also shows how user can define their own functional coverage groups.You can install the example wi
2012-01-29 17:56:50
2568
转载 AXI VIP 中定义自己的define文件
Normally, the interface file “axi_if.sv “ includes a” AxiPortDefines.inc” file , which has lots of `defines with default values, and may mismatch with your real design. `define DW_VIP_AXI_ADDR_POR
2012-01-29 17:54:10
1165
转载 AXI Slave VIP that control the delay between the AREADY and AVALID
There are two variables in AXI Slave VIP that control the delay between the AREADY and AVALID: MAX: dw_vip_axi_port_configuration :: m_nMaxDelay = 5000 MIN: m_nAvalidAreadyDelay = 0;
2012-01-29 17:45:15
1504
原创 assertions 使用问答
1. 如何防止在simulation结束仍然还未结束的assertion打印出消息？VCS supports disabling the SVA unfinished message reporting at the end of simulation, please do as follows:1) Add VCS compile option “vcs -assert
2012-01-21 22:17:24
2769
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