PCI-Express 16x

 

The PCI-Express bus supports 1x [2.5Gbps], 2x, 4x, 8x, 12x, 16x, and 32x bus widths [transmit / receive pairs].
The PCI-Express [PCIe] 16x signal names and pinout are listed in the table below.
The 16x wide PCI Express bus is used as the video expansion slot on PC motherboards, replacing the older and slower AGP video slot.
The pinout table below provides 16 transmit pairs and 16 receive signal pairs [signals are differential] for a signal through-put of 5GBps.
Pinout tables for the other PCI Express widths are listed below the table.





PCI-Express 16x PinOut
PinSide B ConnectorSide A Connector
#NameDescriptionNameDescription
1+12v+12 volt powerPRSNT#1Hot plug presence detect
2+12v+12 volt power+12v+12 volt power
3+12v+12 volt power+12v+12 volt power
4GNDGroundGNDGround
5SMCLKSMBus clockJTAG2TCK
6SMDATSMBus dataJTAG3TDI
7GNDGroundJTAG4TDO
8+3.3v+3.3 volt powerJTAG5TMS
9JTAG1+TRST#+3.3v+3.3 volt power
103.3Vaux3.3v volt power+3.3v+3.3 volt power
11WAKE#Link ReactivationPWRGDPower Good
Mechanical Key
12RSVDReservedGNDGround
13GNDGroundREFCLK+Reference Clock
Differential pair
14HSOp(0)Transmitter Lane 0,
Differential pair
REFCLK-
15HSOn(0)GNDGround
16GNDGroundHSIp(0)Receiver Lane 0,
Differential pair
17PRSNT#2Hotplug detectHSIn(0)
18GNDGroundGNDGround
19HSOp(1)Transmitter Lane 1,
Differential pair
RSVDReserved
20HSOn(1)GNDGround
21GNDGroundHSIp(1)Receiver Lane 1,
Differential pair
22GNDGroundHSIn(1)
23HSOp(2)Transmitter Lane 2,
Differential pair
GNDGround
24HSOn(2)GNDGround
25GNDGroundHSIp(2)Receiver Lane 2,
Differential pair
26GNDGroundHSIn(2)
27HSOp(3)Transmitter Lane 3,
Differential pair
GNDGround
28HSOn(3)GNDGround
29GNDGroundHSIp(3)Receiver Lane 3,
Differential pair
30RSVDReservedHSIn(3)
31PRSNT#2Hot plug detectGNDGround
32GNDGroundRSVDReserved
33HSOp(4)Transmitter Lane 4,
Differential pair
RSVDReserved
34HSOn(4)GNDGround
35GNDGroundHSIp(4)Receiver Lane 4,
Differential pair
36GNDGroundHSIn(4)
37HSOp(5)Transmitter Lane 5,
Differential pair
GNDGround
38HSOn(5)GNDGround
39GNDGroundHSIp(5)Receiver Lane 5,
Differential pair
40GNDGroundHSIn(5)
41HSOp(6)Transmitter Lane 6,
Differential pair
GNDGround
42HSOn(6)GNDGround
43GNDGroundHSIp(6)Receiver Lane 6,
Differential pair
44GNDGroundHSIn(6)
45HSOp(7)Transmitter Lane 7,
Differential pair
GNDGround
46HSOn(7)GNDGround
47GNDGroundHSIp(7)Receiver Lane 7,
Differential pair
48PRSNT#2Hot plug detectHSIn(7)
49GNDGroundGNDGround
50HSOp(8)Transmitter Lane 8,
Differential pair
RSVDReserved
51HSOn(8)GNDGround
52GNDGroundHSIp(8)Receiver Lane 8,
Differential pair
53GNDGroundHSIn(8)
54HSOp(9)Transmitter Lane 9,
Differential pair
GNDGround
55HSOn(9)GNDGround
56GNDGroundHSIp(9)Receiver Lane 9,
Differential pair
57GNDGroundHSIn(9)
58HSOp(10)Transmitter Lane 10,
Differential pair
GNDGround
59HSOn(10)GNDGround
60GNDGroundHSIp(10)Receiver Lane 10,
Differential pair
61GNDGroundHSIn(10)
62HSOp(11)Transmitter Lane 11,
Differential pair
GNDGround
63HSOn(11)GNDGround
64GNDGroundHSIp(11)Receiver Lane 11,
Differential pair
65GNDGroundHSIn(11)
66HSOp(12)Transmitter Lane 12,
Differential pair
GNDGround
67HSOn(12)GNDGround
68GNDGroundHSIp(12)Receiver Lane 12,
Differential pair
69GNDGroundHSIn(12)
70HSOp(13)Transmitter Lane 13,
Differential pair
GNDGround
71HSOn(13)GNDGround
72GNDGroundHSIp(13)Receiver Lane 13,
Differential pair
73GNDGroundHSIn(13)
74HSOp(14)Transmitter Lane 14,
Differential pair
GNDGround
75HSOn(14)GNDGround
76GNDGroundHSIp(14)Receiver Lane 14,
Differential pair
77GNDGroundHSIn(14)
78HSOp(15)Transmitter Lane 15,
Differential pair
GNDGround
79HSOn(15)GNDGround
80GNDGroundHSIp(15)Receiver Lane 15,
Differential pair
81PRSNT#2Hot plug present detectHSIn(15)
82RSVD#2Hot Plug DetectGNDGround




PCI Express is the new serial bus addition to the PCI series of specifications. This is a serial bus which uses two low-voltage differential LVDS pairs, at 2.5Gb/s in each direction [one transmit, and one receive pair]. PCI Express uses8B/10B encoding [each 8 bit byte is translated into a 10 bit character in order to equalize the numbers of 1's and 0's sent, and the encoded signal contains an embedded clock]. PCI Express supports 1x [2.5Gbps], 2x, 4x, 8x, 12x, 16x, and 32x bus widths [transmit / receive pairs]. The PCI-Express [PCIe] 16x signal names and pinout are listed above.

The differential pins [Lanes] listed in the pin out table above are LVDS which stands for: Low Voltage Differential Signaling. The Electrical layer of LVDS is described on the LVDS bus page. The function of the JTAG pins listed above are described on the JTAG bus page.
The function of the SMbus pins are described on the SMbus page.

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