S5PV210有两个独立的DRAM控制器，分别是DMC0和DMC1，其中，DMC0最大支持512MByte，DMC1最大支持1GByte，而DMC0和DMC1又同时支持两个片选CS0和CS1。S5PV210的内存模块相比2440和6410来讲要更加复杂一些，要想正确的配置S5PV210的内存，应该仔细阅读芯片手册相关部分，在配置参数时也应该适当的阅读下内存芯片的手册。这部分的寄存器和配置过程比较复杂（但是不难），我只简单的讲一下我配置时遇到的问题。
一 接线原理
我的开发板是TQ210，开发板上有8片128M*8bits的内存芯片，从原理图上可以看到，其中4片并联接在DMC0上，另外四片并联在DMC1上，这里我只贴出一个链接方式，因为8片都是一样的，只是前四片跟后四片挂载的位置不同。
我们可以注意到，TQ210是将四片K4T1G084QQ的地址线并联，将数据线串联，这样正好是32位数据。另外，我们还可以看到K4T1G084QQ只接了14根地址线，这是因为K4T1G084QQ有14根行地址，10根列地址，这14根线是复用的。但是K4T1G084QQ有8个bank，而DMC只有两根bank线，为此，S5PV210给出了以下几个解决方案：
根据注释3，我们可以看到当S5PV210挂载8bank内存时CS1复用为BANK2，这中状态下S5PV210相当于只有一根片选引脚CS0，这样就可以理解了，我们从这里也可以知道配置num_chip参数时可以设置为1（经测试设置为2也可以，不过MEMCONFIG1的配置没有意思，因为8bank时只有CS0而没有CS1）。对于8banks且15根行地址的内存芯片也有一套解决方案，所以，一定要注意下面的注释，我当时配置时阅读手册就不够仔细，没有看下面的注释，结果卡了我一上午，没有弄明白内存芯片的接线原理，甚至认为开发板接线接错了。
二 地址映射
S5PV210的DMC跟6410和2440的DMC有个重要区别，S5PV210可以控制内存地址映射，DMC0的地址空间为0x2000,0000~0x3fff,ffff，DMC1的地址空间为0x4000,0000~0x7fff,ffff，DMC可以通过配置寄存器来使内存芯片映射到其内存段内的适当位置。这个配置在MEMCONFIG寄存器中，这个地址映射让我纠结了很长一段时间，最后还是查资料看明白的。
如果设置chip_base为0x20：
(1)我们挂载的内存为128M，那么这个chip_mask应该设置为0xF8
(2)我们挂载256M内存时，chip_mask应该设置为0xF0
(3)我们挂载512M时，chip_mask应该设置为0xE0
(4)我们挂载1GB内存时，chip_mask就应该设置为0xC0。
以DMC0为例，当DMC0接收到来自AXI的0x2000,0000~0x3fff,ffff内的地址时，会作如下处理：
(1)将AXI地址的高8位与chip_mask相与得到结果，记为X。
(2)将X分别与MEMCONFIG0和MEMCONFIG1的chip_base相比较，如果相等，则打开相应的片选。
假如挂载的内存为128M，且CS0和CS1上分别挂了一片，那么128M=128*1024*1024=0x8000000，则128M内存的偏移范围应该是0x0000,0000~0x07ff,ffff，高位剩余5位，那么，我们把MEMCONFIG0的chip_base设置为0x20，chip_mask设置为0xF8，为了保持内存连续，则需要将MEMCONFIG1的chip_base设置为0x28，chip_mask设置为0xF8，当AXI发来的地址为0x23xx,xxxx时，0x23&0xF8得到0x20，所以，会打开片选CS0，当AXI发来的地址为0x28xx,xxxx时，0x28&0xF8得到0x28，所以，会打开片选CS1，依此类推。
特别的，当载在的内存芯片为8bank（8bank内存芯片一般为14/15行地址，10列地址，即容量一般为512M或者1G）时，由于CS1为bank2引脚，为了保持CS0时钟处于片选状态，对于512M内存来讲需要将chip_mask设置为0xE0，这是因为512M=512*1024*1024=0x2000,0000，也就是说，512M内存的偏移应该为0x0000,0000~0x1fff,ffff，所以高位剩余3位，即0xE0，当然了，如果内存为1G=1024*1024*1024=0x4000,0000，即偏移为0x0000,0000~0x3fff,ffff，高位剩余2为，故设置chip_mask为0xC0。这样，就会计算偏移这两个值了。
三 配置流程
内存芯片的配置比较复杂，好在芯片手册上给出了常用内存类型的初始化序列，TQ210的内存是DDR2的，可以按照如下顺序进行初始化：
- 1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.
- 2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_on bit-field to ‘1’ to turn on the PHY DLL.
- 3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value according to clock frequency and memory tAC parameters.
- 4. Set the PhyControl0.ctrl_start bit-field to ‘1’.
- 5. Set the ConControl. At this moment, an auto refresh counter should be off.
- 6. Set the MemControl. At this moment, all power down modes should be off.
- 7. Set the MemConfig0 register. If there are two external memo ry chips, set the MemConfig1 register.
- 8. Set the PrechConfig and PwrdnConfig registers.
- 9. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC parameters.
- 10. If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers.
- 11. Wait for the PhyStatus0.ctrl_locked bit-fields to change to ‘1’. Check whether PHY DLL is locked.
- 12. PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT) variation during memory operation. Therefore, PHY DLL should not be off for reliable operation. It can be off except runs at low frequency. If off mode is used, set the PhyControl0.ctrl_force bit-field to correct value according to the PhyStatus0.ctrl_lock_value[9:2] bit-field to fix delay amount. Clear the PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL.
- 13. Confirm whether stable clock is issued minimum 200us after power on
- 14. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level
- 15. Wait for minimum 400ns.
- 16. Issue a PALL command using the DirectCmd register.
- 17. Issue an EMRS2 command using the DirectCmd register to program the operating parameters.
- 18. Issue an EMRS3 command using the DirectCmd register to program the operating parameters.
- 19. Issue an EMRS command using the DirectCmd register to enable the memory DLLs.
- 20. Issue a MRS command using the DirectCmd register to reset the memory DLL.
- 21. Issue a PALL command using the DirectCmd register.
- 22. Issue two Auto Refresh commands using the DirectCmd register.
- 23. Issue a MRS command using the DirectCmd register to program the operating parameters without resetting the memory DLL.
- 24. Wait for minimum 200 clock cycles.
- 25. Issue an EMRS command using the DirectCmd register to program the operating parameters. If OCD calibration is not used, issue an EMRS command to set OCD Calibration Default. After that, issue an EMRS command to exit OCD Calibration Mode and to program the operating parameters.
- 26. If there are two external memory chips, perform steps 14~25 for chip1 memory device.
- 27. Set the ConControl to turn on an auto refresh counter. 28. If power down modes is required, set the MemControl registers.
1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.
2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_on bit-field to ‘1’ to turn on the PHY DLL.
3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value according to clock frequency and memory tAC parameters.
4. Set the PhyControl0.ctrl_start bit-field to ‘1’.
5. Set the ConControl. At this moment, an auto refresh counter should be off.
6. Set the MemControl. At this moment, all power down modes should be off.
7. Set the MemConfig0 register. If there are two external memo ry chips, set the MemConfig1 register.
8. Set the PrechConfig and PwrdnConfig registers.
9. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC parameters.
10. If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers.
11. Wait for the PhyStatus0.ctrl_locked bit-fields to change to ‘1’. Check whether PHY DLL is locked.
12. PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT) variation during memory operation. Therefore, PHY DLL should not be off for reliable operation. It can be off except runs at low frequency. If off mode is used, set the PhyControl0.ctrl_force bit-field to correct value according to the PhyStatus0.ctrl_lock_value[9:2] bit-field to fix delay amount. Clear the PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL.
13. Confirm whether stable clock is issued minimum 200us after power on
14. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level
15. Wait for minimum 400ns.
16. Issue a PALL command using the DirectCmd register.
17. Issue an EMRS2 command using the DirectCmd register to program the operating parameters.
18. Issue an EMRS3 command using the DirectCmd register to program the operating parameters.
19. Issue an EMRS command using the DirectCmd register to enable the memory DLLs.
20. Issue a MRS command using the DirectCmd register to reset the memory DLL.
21. Issue a PALL command using the DirectCmd register.
22. Issue two Auto Refresh commands using the DirectCmd register.
23. Issue a MRS command using the DirectCmd register to program the operating parameters without resetting the memory DLL.
24. Wait for minimum 200 clock cycles.
25. Issue an EMRS command using the DirectCmd register to program the operating parameters. If OCD calibration is not used, issue an EMRS command to set OCD Calibration Default. After that, issue an EMRS command to exit OCD Calibration Mode and to program the operating parameters.
26. If there are two external memory chips, perform steps 14~25 for chip1 memory device.
27. Set the ConControl to turn on an auto refresh counter. 28. If power down modes is required, set the MemControl registers.四 内存初始化代码
我将我配置内存的代码上传到CSDN的下载空间，如果需要的话可以去我资源里下载，是C语言版的。
五 遗留问题
配置好内存的代码烧写到Nand运行是正常的，但是用USB方式启动时不正常，目前还没有找到原因，如果有朋友解决了或者有其他问题请留言相告，在这里先说声谢谢。
现在找到原因了，原来S5PV210的USB启动过程跟Nand启动方式不一样，S5PV210以USB方式启动时会先将三星提供的一个固件程序下载到0xd0020010处运行，然后，再将用户代码下载0x23e00000处运行，也就是说，固件程序完成了内存的初始化，因为我们的代码位于0x23e00000处。而我们的代码中再次配置内存时会重置内存，下载到内存中的代码也就丢失了，所以程序执行到内存初始化函数就会挂掉。
为了证明上面的假设，我在代码中加上一段程序，该程序将内存的中代码拷贝到iram的16K以后的位置上（直接拷贝到0xd0020000处有问题，我是拷贝到了0xd0024000处，现在还不知道什么原因），然后将代码跳转到IRAM中，如果代码可以正常运行就可以证明内存初始化部分正常，实验结果是肯定的，下面总结下：
S5PV210以USB方式启动时用户代码是下载到内存中的（0x23e00000处），要使代码以USB方式启动时正常运行，应该注意以下两点：
（1）如果是位置相关的代码，连接地址应该链接到0x23e00000，如果是位置无关码，可以随便指定连接地址。
（2）用户代码需要检验自己运行时的位置，如果运行在内存中则需跳过内存初始化，根据需要决定是否需要代码重定位。
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