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Xilinx Processor IP Library

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typedef unsigned char   Xuint8;     /**< unsigned 8-bit */
typedef char            Xint8;      /**< signed 8-bit */
typedef unsigned short  Xuint16;    /**< unsigned 16-bit */
typedef short           Xint16;     /**< signed 16-bit */
typedef unsigned long   Xuint32;    /**< unsigned 32-bit */
typedef long            Xint32;     /**< signed 32-bit */
typedef float           Xfloat32;   /**< 32-bit floating point */
typedef double          Xfloat64;   /**< 64-bit double precision floating point */
typedef unsigned long   Xboolean;   /**< boolean (XTRUE or XFALSE) */                        

#define XIo_In8(InputPtr)  (*(volatile Xuint8  *)(InputPtr))
#define XIo_Out8(OutputPtr, Value)  { (*(volatile Xuint8  *)(OutputPtr) = Value);  }

#define XGpio_mWriteReg(BaseAddress, RegOffset, Data)  XIo_Out32((BaseAddress) + (RegOffset), (Xuint32)(Data))
#define XGpio_mSetDataReg(BaseAddress, Channel, Data) /
    XGpio_mWriteReg((BaseAddress), /
                    (((Channel) - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET,/
                    (Data))
#define XGpio_mReadReg(BaseAddress, RegOffset) XIo_In32((BaseAddress) + (RegOffset))
#define XGpio_mGetDataReg(BaseAddress, Channel) /
    XGpio_mReadReg((BaseAddress), /
                   (((Channel) - 1) * XGPIO_CHAN_OFFSET) + XGPIO_DATA_OFFSET)

#define XTRUE       1
#define XFALSE      0

#ifndef NULL
#define NULL 0
#endif

#define XNULL NULL

#define XCOMPONENT_IS_READY     0x11111111  /* component has been initialized */
#define XCOMPONENT_IS_STARTED   0x22222222  /* component has been started */

#define XTEST_PASSED    0
#define XTEST_FAILED    1

#define XASSERT_NONE     0
#define XASSERT_OCCURRED 1

extern unsigned int XAssertStatus;
extern void XAssert(char *, int);

typedef struct
{
    Xuint32 Upper;
    Xuint32 Lower;
} Xuint64;


typedef struct
{
    Xuint16  DeviceId;          /* Unique ID  of device */
    Xuint32  BaseAddress;       /* Device base address */
    Xboolean InterruptPresent;  /* Are interrupts supported in h/w */
    Xboolean IsDual;            /* Are 2 channels supported in h/w */
} XGpio_Config;

typedef struct
{
    Xuint32  BaseAddress;   /* Device base address */
    Xuint32  IsReady;       /* Device is initialized and ready */
    XGpio_Config *ConfigPtr;/* Pointer to the configuration */
} XGpio;


typedef struct
{
    Xuint32 TransmitInterrupts;     /**< Number of transmit interrupts */
    Xuint32 ReceiveInterrupts;      /**< Number of receive interrupts */
    Xuint32 CharactersTransmitted;  /**< Number of characters transmitted */
    Xuint32 CharactersReceived;     /**< Number of characters received */
    Xuint32 ReceiveOverrunErrors;   /**< Number of receive overruns */
    Xuint32 ReceiveParityErrors;    /**< Number of receive parity errors */
    Xuint32 ReceiveFramingErrors;   /**< Number of receive framing errors */
} XUartLite_Stats;

/**
 * The following data type is used to manage the buffers that are handled
 * when sending and receiving data in the interrupt mode. It is intended
 * for internal use only.
 */
typedef struct
{
    Xuint8 *NextBytePtr;
    unsigned int RequestedBytes;
    unsigned int RemainingBytes;
} XUartLite_Buffer;

/**
 * This typedef contains configuration information for the device.
 */
typedef struct
{
    Xuint16 DeviceId;       /**< Unique ID  of device */
    Xuint32 RegBaseAddr;    /**< Register base address */
    Xuint32 BaudRate;       /**< Fixed baud rate */
    Xuint8  UseParity;      /**< Parity generator enabled when XTRUE */
    Xuint8  ParityOdd;      /**< Parity generated is odd when XTRUE, even when
                                 XFALSE */
    Xuint8  DataBits;       /**< Fixed data bits */
} XUartLite_Config;

/**
 * The XUartLite driver instance data. The user is required to allocate a
 * variable of this type for every UART Lite device in the system. A pointer
 * to a variable of this type is then passed to the driver API functions.
 */
typedef struct
{
    XUartLite_Stats Stats;      /* Component Statistics */
    Xuint32 RegBaseAddress;     /* Base address of registers */
    Xuint32 IsReady;            /* Device is initialized and ready */


    XUartLite_Buffer SendBuffer;
    XUartLite_Buffer ReceiveBuffer;

    XUartLite_Handler RecvHandler;
    void *RecvCallBackRef;          /* Callback reference for recv handler */
    XUartLite_Handler SendHandler;
    void *SendCallBackRef;          /* Callback reference for send handler */
} XUartLite;


#define XST_SUCCESS                     0L
#define XST_FAILURE                     1L
#define XST_DEVICE_NOT_FOUND            2L
#define XST_DEVICE_BLOCK_NOT_FOUND      3L
#define XST_INVALID_VERSION             4L
#define XST_DEVICE_IS_STARTED           5L
#define XST_DEVICE_IS_STOPPED           6L
#define XST_FIFO_ERROR                  7L  /* an error occurred during an
                                               operation with a FIFO such as
                                               an underrun or overrun, this
                                               error requires the device to
                                               be reset */
#define XST_RESET_ERROR                 8L  /* an error occurred which requires
                                               the device to be reset */
#define XST_DMA_ERROR                   9L  /* a DMA error occurred, this error
                                               typically requires the device
                                               using the DMA to be reset */
#define XST_NOT_POLLED                  10L  /* the device is not configured for
                                               polled mode operation */
#define XST_FIFO_NO_ROOM                11L /* a FIFO did not have room to put
                                               the specified data into */
#define XST_BUFFER_TOO_SMALL            12L /* the buffer is not large enough
                                               to hold the expected data */
#define XST_NO_DATA                     13L /* there was no data available */
#define XST_REGISTER_ERROR              14L /* a register did not contain the
                                               expected value */
#define XST_INVALID_PARAM               15L /* an invalid parameter was passed
                                               into the function */
#define XST_NOT_SGDMA                   16L /* the device is not configured for
                                               scatter-gather DMA operation */
#define XST_LOOPBACK_ERROR              17L /* a loopback test failed */
#define XST_NO_CALLBACK                 18L /* a callback has not yet been
                                             * registered */
#define XST_NO_FEATURE                  19L /* device is not configured with
                                             * the requested feature */
#define XST_NOT_INTERRUPT               20L /* device is not configured for
                                             * interrupt mode operation */
#define XST_DEVICE_BUSY                 21L /* device is busy */
#define XST_ERROR_COUNT_MAX             22L /* the error counters of a device
                                             * have maxed out */
#define XST_IS_STARTED                  23L /* used when part of device is
                                             * already started i.e.
                                             * sub channel */
#define XST_IS_STOPPED                  24L /* used when part of device is
                                             * already stopped i.e.
                                             * sub channel */

/***************** Utility Component statuses 401 - 500  *********************/

#define XST_MEMTEST_FAILED              401L /* memory test failed */


/***************** Common Components statuses 501 - 1000 *********************/

/********************* Packet Fifo statuses 501 - 510 ************************/

#define XST_PFIFO_LACK_OF_DATA          501L   /* not enough data in FIFO   */
#define XST_PFIFO_NO_ROOM               502L   /* not enough room in FIFO   */
#define XST_PFIFO_BAD_REG_VALUE         503L   /* self test, a register value
                                                  was invalid after reset */

/************************** DMA statuses 511 - 530 ***************************/

#define XST_DMA_TRANSFER_ERROR          511L /* self test, DMA transfer
                                                failed */
#define XST_DMA_RESET_REGISTER_ERROR    512L /* self test, a register value
                                                was invalid after reset */
#define XST_DMA_SG_LIST_EMPTY           513L /* scatter gather list contains
                                                no buffer descriptors ready
                                                to be processed */
#define XST_DMA_SG_IS_STARTED           514L /* scatter gather not stopped */
#define XST_DMA_SG_IS_STOPPED           515L /* scatter gather not running */
#define XST_DMA_SG_LIST_FULL            517L /* all the buffer desciptors of
                                                the scatter gather list are
                                                being used */
#define XST_DMA_SG_BD_LOCKED            518L /* the scatter gather buffer
                                                descriptor which is to be
                                                copied over in the scatter
                                                list is locked */
#define XST_DMA_SG_NOTHING_TO_COMMIT    519L /* no buffer descriptors have been
                                                put into the scatter gather
                                                list to be commited */
#define XST_DMA_SG_COUNT_EXCEEDED       521L /* the packet count threshold
                                                specified was larger than the
                                                total # of buffer descriptors
                                                in the scatter gather list */
#define XST_DMA_SG_LIST_EXISTS          522L /* the scatter gather list has
                                                already been created */
#define XST_DMA_SG_NO_LIST              523L /* no scatter gather list has
                                                been created */
#define XST_DMA_SG_BD_NOT_COMMITTED     524L /* the buffer descriptor which was
                                                being started was not committed
                                                to the list */
#define XST_DMA_SG_NO_DATA              525L /* the buffer descriptor to start
                                                has already been used by the
                                                hardware so it can't be reused
                                                */

/************************** IPIF statuses 531 - 550 ***************************/

#define XST_IPIF_REG_WIDTH_ERROR        531L /* an invalid register width
                                                was passed into the function */
#define XST_IPIF_RESET_REGISTER_ERROR   532L /* the value of a register at
                                                reset was not valid */
#define XST_IPIF_DEVICE_STATUS_ERROR    533L /* a write to the device interrupt
                                                status register did not read
                                                back correctly */
#define XST_IPIF_DEVICE_ACK_ERROR       534L /* the device interrupt status
                                                register did not reset when
                                                acked */
#define XST_IPIF_DEVICE_ENABLE_ERROR    535L /* the device interrupt enable
                                                register was not updated when
                                                other registers changed */
#define XST_IPIF_IP_STATUS_ERROR        536L /* a write to the IP interrupt
                                                status register did not read
                                                back correctly */
#define XST_IPIF_IP_ACK_ERROR           537L /* the IP interrupt status register
                                                did not reset when acked */
#define XST_IPIF_IP_ENABLE_ERROR        538L /* IP interrupt enable register was
                                                not updated correctly when other
                                                registers changed */
#define XST_IPIF_DEVICE_PENDING_ERROR   539L /* The device interrupt pending
                                                register did not indicate the
                                                expected value */
#define XST_IPIF_DEVICE_ID_ERROR        540L /* The device interrupt ID register
                                                did not indicate the expected
                                                value */

/****************** Device specific statuses 1001 - 4095 *********************/

/********************* Ethernet statuses 1001 - 1050 *************************/

#define XST_EMAC_MEMORY_SIZE_ERROR  1001L /* Memory space is not big enough
                                           * to hold the minimum number of
                                           * buffers or descriptors */
#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
#define XST_EMAC_MII_READ_ERROR     1003L /* MII read error */
#define XST_EMAC_MII_BUSY           1004L /* An MII operation is in progress */
#define XST_EMAC_OUT_OF_BUFFERS     1005L /* Adapter is out of buffers */
#define XST_EMAC_PARSE_ERROR        1006L /* Invalid adapter init string */
#define XST_EMAC_COLLISION_ERROR    1007L /* Excess deferral or late
                                           * collision on polled send */

/*********************** UART statuses 1051 - 1075 ***************************/
#define XST_UART

#define XST_UART_INIT_ERROR         1051L
#define XST_UART_START_ERROR        1052L
#define XST_UART_CONFIG_ERROR       1053L
#define XST_UART_TEST_FAIL          1054L
#define XST_UART_BAUD_ERROR         1055L
#define XST_UART_BAUD_RANGE         1056L


/************************ IIC statuses 1076 - 1100 ***************************/

#define XST_IIC_SELFTEST_FAILED         1076 /* self test failed            */
#define XST_IIC_BUS_BUSY                1077 /* bus found busy              */
#define XST_IIC_GENERAL_CALL_ADDRESS    1078 /* mastersend attempted with   */
                                             /* general call address        */
#define XST_IIC_STAND_REG_RESET_ERROR   1079 /* A non parameterizable reg   */
                                             /* value after reset not valid */
#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design  */
                                             /* value after reset not valid */
#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design  */
                                             /* value after reset not valid */
#define XST_IIC_TBA_REG_RESET_ERROR     1082 /* 10 bit addr incl in design  */
                                             /* value after reset not valid */
#define XST_IIC_CR_READBACK_ERROR       1083 /* Read of the control register*/
                                             /* didn't return value written */
#define XST_IIC_DTR_READBACK_ERROR      1084 /* Read of the data Tx reg     */
                                             /* didn't return value written */
#define XST_IIC_DRR_READBACK_ERROR      1085 /* Read of the data Receive reg*/
                                             /* didn't return value written */
#define XST_IIC_ADR_READBACK_ERROR      1086 /* Read of the data Tx reg     */
                                             /* didn't return value written */
#define XST_IIC_TBA_READBACK_ERROR      1087 /* Read of the 10 bit addr reg */
                                             /* didn't return written value */
#define XST_IIC_NOT_SLAVE               1088 /* The device isn't a slave    */

/*********************** ATMC statuses 1101 - 1125 ***************************/

#define XST_ATMC_ERROR_COUNT_MAX    1101L   /* the error counters in the ATM
                                               controller hit the max value
                                               which requires the statistics
                                               to be cleared */

/*********************** Flash statuses 1126 - 1150 **************************/

#define XST_FLASH_BUSY                1126L /* Flash is erasing or programming */
#define XST_FLASH_READY               1127L /* Flash is ready for commands */
#define XST_FLASH_ERROR               1128L /* Flash had detected an internal
                                               error. Use XFlash_DeviceControl
                                               to retrieve device specific codes */
#define XST_FLASH_ERASE_SUSPENDED     1129L /* Flash is in suspended erase state */
#define XST_FLASH_WRITE_SUSPENDED     1130L /* Flash is in suspended write state */
#define XST_FLASH_PART_NOT_SUPPORTED  1131L /* Flash type not supported by
                                               driver */
#define XST_FLASH_NOT_SUPPORTED       1132L /* Operation not supported */
#define XST_FLASH_TOO_MANY_REGIONS    1133L /* Too many erase regions */
#define XST_FLASH_TIMEOUT_ERROR       1134L /* Programming or erase operation
                                               aborted due to a timeout */
#define XST_FLASH_ADDRESS_ERROR       1135L /* Accessed flash outside its
                                               addressible range */
#define XST_FLASH_ALIGNMENT_ERROR     1136L /* Write alignment error */
#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
                                               write/erase function with
                                               XFL_NON_BLOCKING_WRITE/ERASE
                                               option cleared */
#define XST_FLASH_CFI_QUERY_ERROR     1138L /* Failed to query the device */

/*********************** SPI statuses 1151 - 1175 ****************************/
#define XST_SPI_MODE_FAULT          1151 /* master was selected as slave */
#define XST_SPI_TRANSFER_DONE       1152 /* data transfer is complete */
#define XST_SPI_TRANSMIT_UNDERRUN   1153 /* slave underruns transmit register */
#define XST_SPI_RECEIVE_OVERRUN     1154 /* device overruns receive register */
#define XST_SPI_NO_SLAVE            1155 /* no slave has been selected yet */
#define XST_SPI_TOO_MANY_SLAVES     1156 /* more than one slave is being
                                          * selected */
#define XST_SPI_NOT_MASTER          1157 /* operation is valid only as master */
#define XST_SPI_SLAVE_ONLY          1158 /* device is configured as slave-only */
#define XST_SPI_SLAVE_MODE_FAULT    1159 /* slave was selected while disabled */

/********************** OPB Arbiter statuses 1176 - 1200 *********************/

#define XST_OPBARB_INVALID_PRIORITY  1176 /* the priority registers have either
                                           * one master assigned to two or more
                                           * priorities, or one master not
                                           * assigned to any priority
                                           */
#define XST_OPBARB_NOT_SUSPENDED     1177 /* an attempt was made to modify the
                                           * priority levels without first
                                           * suspending the use of priority
                                           * levels
                                           */
#define XST_OPBARB_PARK_NOT_ENABLED  1178 /* bus parking by id was enabled but
                                           * bus parking was not enabled
                                           */
#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
                                            * priority mode to allow the
                                            * priorities to be changed
                                            */

/************************ Intc statuses 1201 - 1225 **************************/

#define XST_INTC_FAIL_SELFTEST      1201        /* self test failed */
#define XST_INTC_CONNECT_ERROR      1202        /* interrupt already in use */

/********************** TmrCtr statuses 1226 - 1250 **************************/

#define XST_TMRCTR_TIMER_FAILED     1226        /* self test failed */

/********************** WdtTb statuses 1251 - 1275 ***************************/

#define XST_WDTTB_TIMER_FAILED      1251L

/********************** PlbArb statuses 1276 - 1300 **************************/

#define XST_PLBARB_FAIL_SELFTEST    1276L

/********************** Plb2Opb statuses 1301 - 1325 *************************/

#define XST_PLB2OPB_FAIL_SELFTEST   1301L

/********************** Opb2Plb statuses 1326 - 1350 *************************/

#define XST_OPB2PLB_FAIL_SELFTEST   1326L

/********************** SysAce statuses 1351 - 1360 **************************/

#define XST_SYSACE_NO_LOCK          1351L    /* No MPU lock has been granted */

/********************** PCI Bridge statuses 1361 - 1375 **********************/

#define XST_PCI_INVALID_ADDRESS     1361L

/**************************** Type Definitions *******************************/

/**
 * The status typedef.
 */
typedef Xuint32 XStatus;


/*****************************************************************************
 *
 * System Level defines. These constants are for devices that do not require
 * a device driver. Examples of these types of devices include volatile RAM
 * devices.
 */
#define XPAR_ZBT_NUM_INSTANCES   1
#define XPAR_ZBT_0_BASE          0x00000000
#define XPAR_ZBT_0_SIZE          0x00100000

#define XPAR_SRAM_NUM_INSTANCES  1
#define XPAR_SRAM_0_BASE         0x00100000
#define XPAR_SRAM_0_SIZE         0x00200000

#define XPAR_DDR_NUM_INSTANCES   1
#define XPAR_DDR_0_BASE          0xF0000000
#define XPAR_DDR_0_SIZE          0x01000000

#define XPAR_CORE_CLOCK_FREQ_HZ  12500000

#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ  XPAR_CORE_CLOCK_FREQ_HZ

/*****************************************************************************
 *
 * Interrupt Controller (Intc) defines.
 * DeviceID starts at 0
 */
#define XPAR_XINTC_NUM_INSTANCES        2          /* Number of instances */
#define XPAR_INTC_MAX_NUM_INTR_INPUTS  31         /* max # inputs of all */
#define XPAR_INTC_SINGLE_BASEADDR      0x70800000 /* low level driver base */
#define XPAR_INTC_SINGLE_DEVICE_ID     0          /* single instance ID */
#define XPAR_INTC_SINGLE_ACK_BEFORE    0xFFFF00FF /* low level driver */

#define XPAR_INTC_0_DEVICE_ID          1          /* Device ID for instance */
#define XPAR_INTC_0_ACK_BEFORE         0xFFFF00FF /* Ack timing, before/after */
#define XPAR_INTC_0_BASEADDR           0x70800000 /* Register base address */

#define XPAR_INTC_0_UARTLITE_0_VEC_ID  4          /* Interrupt source for vector */
#define XPAR_INTC_0_WDTTB_0_VEC_ID     5          /* Interrupt source for vector */
#define XPAR_INTC_0_WD_0_VEC_ID        6          /* Interrupt source for vector */
#define XPAR_INTC_0_TMRCTR_0_VEC_ID    7          /* Interrupt source for vector */
#define XPAR_INTC_0_SPI_0_VEC_ID       11         /* Interrupt source for vector */
#define XPAR_INTC_0_IIC_0_VEC_ID       12         /* Interrupt source for vector */
#define XPAR_INTC_0_UARTNS550_0_VEC_ID 13         /* Interrupt source for vector */
#define XPAR_INTC_0_UARTNS550_1_VEC_ID 14         /* Interrupt source for vector */
#define XPAR_INTC_0_EMAC_0_VEC_ID      15         /* Interrupt source for vector */

#define XPAR_INTC_1_DEVICE_ID          2          /* Device ID for instance */
#define XPAR_INTC_1_ACK_BEFORE         0xFFFF00FF /* Ack timing, before/after */
#define XPAR_INTC_1_BASEADDR           0x70800020 /* Register base address */

#define XPAR_INTC_1_OPB_TO_PLB_ERR_VEC_ID 0       /* Interrupt source for vector */
#define XPAR_INTC_1_PLB_TO_OPB_ERR_VEC_ID 1       /* Interrupt source for vector */

/*****************************************************************************
 *
 * Ethernet 10/100 MAC defines.
 * DeviceID starts at 10
 */
#define XPAR_XEMAC_NUM_INSTANCES      1          /* Number of instances */

#define XPAR_EMAC_0_DEVICE_ID        10         /* Device ID for instance */
#define XPAR_EMAC_0_BASEADDR         0x60000000 /* Device base address */
#define XPAR_EMAC_0_DMA_PRESENT      XFALSE     /* Does device have DMA? */
#define XPAR_EMAC_0_ERR_COUNT_EXIST  XTRUE      /* Does device have counters? */
#define XPAR_EMAC_0_MII_EXIST        XTRUE      /* Does device support MII? */

/*****************************************************************************
 *
 * NS16550 UART defines.
 * DeviceID starts at 20
 */
#define XPAR_XUARTNS550_NUM_INSTANCES 1          /* Number of instances */

#define XPAR_UARTNS550_0_DEVICE_ID   20         /* Device ID for instance */
#define XPAR_UARTNS550_0_BASEADDR    0xA0010000 /* IPIF base address */
#define XPAR_UARTNS550_0_CLOCK_HZ    (66000000L)/* 66 MHz clock */

#define XPAR_UARTNS550_1_DEVICE_ID   21         /* Device ID for instance */
#define XPAR_UARTNS550_1_BASEADDR    0xA0000000 /* IPIF base address */
#define XPAR_UARTNS550_1_CLOCK_HZ    (66000000L)/* 66 MHz clock */

/*****************************************************************************
 *
 * UartLite defines.
 * DeviceID starts at 30
 */
#define XPAR_XUARTLITE_NUM_INSTANCES 1         /* Number of instances */

#define XPAR_UARTLITE_0_DEVICE_ID   30         /* Device ID for instance */
#define XPAR_UARTLITE_0_BASEADDR    0xA0020000 /* Device base address */
#define XPAR_UARTLITE_0_BAUDRATE    19200      /* Baud rate */
#define XPAR_UARTLITE_0_USE_PARITY  XFALSE     /* Parity generator enabled */
#define XPAR_UARTLITE_0_ODD_PARITY  XFALSE     /* Type of parity generated */
#define XPAR_UARTLITE_0_DATA_BITS   8          /* Data bits */

/*****************************************************************************
 *
 * ATM controller defines.
 * DeviceID starts at 40
 */
#define XPAR_XATMC_NUM_INSTANCES     1         /* Number of instances */

#define XPAR_ATMC_0_DEVICE_ID       40         /* Device ID for instance */
#define XPAR_ATMC_0_BASEADDR        0x70000000 /* Device base address */
#define XPAR_ATMC_0_DMA_PRESENT     XFALSE     /* Does device have DMA? */

/*****************************************************************************
 *
 * Serial Peripheral Interface (SPI) defines.
 * DeviceID starts at 50
 */
#define XPAR_XSPI_NUM_INSTANCES      2          /* Number of instances */

#define XPAR_SPI_0_DEVICE_ID        50         /* Device ID for instance */
#define XPAR_SPI_0_BASEADDR         0x50000000 /* Device base address */
#define XPAR_SPI_0_FIFO_EXIST       XTRUE      /* Does device have FIFOs? */
#define XPAR_SPI_0_SLAVE_ONLY       XFALSE     /* Is the device slave only? */
#define XPAR_SPI_0_NUM_SS_BITS      32         /* Number of slave select bits */

#define XPAR_SPI_1_DEVICE_ID        51         /* Device ID for instance */
#define XPAR_SPI_1_BASEADDR         0x50000100 /* IPIF base address */
#define XPAR_SPI_1_FIFO_EXIST       XTRUE      /* Does device have FIFOs? */
#define XPAR_SPI_1_SLAVE_ONLY       XFALSE     /* Is the device slave only? */
#define XPAR_SPI_1_NUM_SS_BITS      32         /* Number of slave select bits */

/*****************************************************************************
 *
 * OPB Arbiter defines.
 * DeviceID starts at 60
 */
#define XPAR_XOPBARB_NUM_INSTANCES 1           /* Number of instances */

#define XPAR_OPBARB_0_DEVICE_ID    60         /* Device ID for instance */
#define XPAR_OPBARB_0_BASEADDR     0x80000000 /* Register base address */
#define XPAR_OPBARB_0_NUM_MASTERS  8          /* Number of masters on bus */

/*****************************************************************************
 *
 * Watchdog timer/timebase (WdtTb) defines.
 * DeviceID starts at 70
 */
#define XPAR_XWDTTB_NUM_INSTANCES   1          /* Number of instances */

#define XPAR_WDTTB_0_DEVICE_ID      70         /* Device ID for instance */
#define XPAR_WDTTB_0_BASEADDR       0x70800040 /* Register base address */

/*****************************************************************************
 *
 * Timer Counter (TmrCtr) defines.
 * DeviceID starts at 80
 */
#define XPAR_XTMRCTR_NUM_INSTANCES  2          /* Number of instances */

#define XPAR_TMRCTR_0_DEVICE_ID     80         /* Device ID for instance */
#define XPAR_TMRCTR_0_BASEADDR      0x70800100 /* Register base address */

/*****************************************************************************
 *
 * IIC defines.
 * DeviceID starts at 90
 */
#define XPAR_XIIC_NUM_INSTANCES      2          /* Number of instances */

#define XPAR_IIC_0_DEVICE_ID        90         /* Device ID for instance */
#define XPAR_IIC_0_BASEADDR         0xA8000000 /* Device base address */
#define XPAR_IIC_0_TEN_BIT_ADR      XTRUE      /* Supports 10 bit addresses */

#define XPAR_IIC_1_DEVICE_ID        91         /* Device ID for instance */
#define XPAR_IIC_1_BASEADDR         0xA8000000 /* Device base address */
#define XPAR_IIC_1_TEN_BIT_ADR      XTRUE      /* Supports 10 bit addresses */

/*****************************************************************************
 *
 * Flash defines.
 * DeviceID starts at 100
 */
#define XPAR_XFLASH_NUM_INSTANCES    1          /* Number of instances */
#define XPAR_FLASH_INTEL_SUPPORT               /* Include intel flash support */

#define XPAR_FLASH_0_DEVICE_ID      100        /* Device ID for first instance */
#define XPAR_FLASH_0_BASEADDR       0xFF000000 /* Base address of parts */
#define XPAR_FLASH_0_NUM_PARTS      2          /* Number of parts in array */
#define XPAR_FLASH_0_PART_WIDTH     2          /* Width of each part in bytes */
#define XPAR_FLASH_0_PART_MODE      2          /* Mode of each part in bytes */

/*****************************************************************************
 *
 * GPIO defines.
 * DeviceID starts at 110
 */
#define XPAR_XGPIO_NUM_INSTANCES    1

#define XPAR_GPIO_0_DEVICE_ID       110        /* Device ID for instance */
#define XPAR_GPIO_0_BASEADDR        0x90000000 /* Register base address */
#define XPAR_GPIO_0_INTERRUPT_PRESENT   0      /* Interrupts supported? */
#define XPAR_GPIO_0_IS_DUAL             0      /* Dual channels supported? */

/*****************************************************************************
 *
 * EMC defines.
 * DeviceID starts at 120
 */
#define XPAR_XEMC_NUM_INSTANCES     1

#define XPAR_EMC_0_DEVICE_ID       120         /* Device ID for instance */
#define XPAR_EMC_0_BASEADDR        0xE0000000  /* Register base address */
#define XPAR_EMC_0_NUM_BANKS_MEM   3           /* Number of banks */

/*****************************************************************************
 *
 * PLB Arbiter defines.
 * DeviceID starts at 130
 */
#define XPAR_XPLBARB_NUM_INSTANCES     1

#define XPAR_PLBARB_0_DEVICE_ID       130         /* Device ID for instance */
#define XPAR_PLBARB_0_BASEADDR        0x300       /* Register base address */
#define XPAR_PLBARB_0_NUM_MASTERS     1           /* Number of masters on bus */

/*****************************************************************************
 *
 * PLB To OPB Bridge defines.
 * DeviceID starts at 140
 */
#define XPAR_XPLB2OPB_NUM_INSTANCES     1

#define XPAR_PLB2OPB_0_DEVICE_ID       140         /* Device ID for instance */
#define XPAR_PLB2OPB_0_DCR_BASEADDR    0x0         /* DCR Register base address */
#define XPAR_PLB2OPB_0_NUM_MASTERS       1         /* Number of masters on bus */


/*****************************************************************************
 *
 * OPB To PLB Bridge defines.
 * DeviceID starts at 150
 */
#define XPAR_XOPB2PLB_NUM_INSTANCES     1
#define XPAR_XOPB2PLB_ANY_OPB_REG_INTF       /* Accessible from OPB, not DCR */

#define XPAR_OPB2PLB_0_DEVICE_ID       150   /* Device ID for instance */
#define XPAR_OPB2PLB_0_OPB_BASEADDR    0x0   /* Register base address */
#define XPAR_OPB2PLB_0_DCR_BASEADDR    0x0   /* DCR Register base address */


/*****************************************************************************
 *
 * System ACE defines.
 * DeviceID starts at 160
 */
#define XPAR_XSYSACE_NUM_INSTANCES    1

#define XPAR_SYSACE_0_DEVICE_ID       160         /* Device ID for instance */
#define XPAR_SYSACE_0_BASEADDR        0xCF000000  /* Register base address */


/*****************************************************************************
 *
 * HDLC defines.
 * DeviceID starts at 170
 */
#define XPAR_XHDLC_NUM_INSTANCES     1

#define XPAR_HDLC_0_DEVICE_ID       170             /* Device ID for instance */
#define XPAR_HDLC_0_BASEADDR        0x60010000      /* Register base address */
#define XPAR_HDLC_0_TX_MEM_DEPTH    2048            /* Tx FIFO depth (bytes) */
#define XPAR_HDLC_0_RX_MEM_DEPTH    2048            /* Rx FIFO depth (bytes) */
#define XPAR_HDLC_0_DMA_PRESENT     3               /* DMA SG in hardware */


/*****************************************************************************
 *
 * PS2 Reference driver defines.
 * DeviceID starts at 180
 */
#define XPAR_XPS2_NUM_INSTANCES    2

#define XPAR_PS2_0_DEVICE_ID       180             /* Device ID for instance */
#define XPAR_PS2_0_BASEADDR        0x40010000      /* Register base address */

#define XPAR_PS2_1_DEVICE_ID       181             /* Device ID for instance */
#define XPAR_PS2_1_BASEADDR        0x40020000      /* Register base address */

/*****************************************************************************
 *
 * Rapid IO defines.
 * DeviceID starts at 190
 */
#define XPAR_XRAPIDIO_NUM_INSTANCES    1

#define XPAR_RAPIDIO_0_DEVICE_ID       190             /* Device ID for instance */
#define XPAR_RAPIDIO_0_BASEADDR        0x60000000      /* Register base address */


/*****************************************************************************
 *
 * PCI defines.
 * DeviceID starts at 200
 */
#define XPAR_XPCI_NUM_INSTANCES                      1
#define XPAR_OPB_PCI_1_DEVICE_ID                     200
#define XPAR_OPB_PCI_1_BASEADDR                      0x86000000
#define XPAR_OPB_PCI_1_HIGHADDR                      0x860001FF
#define XPAR_OPB_PCI_1_PCIBAR_0                      0x10000000
#define XPAR_OPB_PCI_1_PCIBAR_LEN_0                  27
#define XPAR_OPB_PCI_1_PCIBAR2IPIF_0                 0xF0000000
#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_0  0
#define XPAR_OPB_PCI_1_PCI_PREFETCH_0                1
#define XPAR_OPB_PCI_1_PCI_SPACETYPE_0               1
#define XPAR_OPB_PCI_1_PCIBAR_1                      0x3F000000
#define XPAR_OPB_PCI_1_PCIBAR_LEN_1                  15
#define XPAR_OPB_PCI_1_PCIBAR2IPIF_1                 0xC0FF8000
#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_1  0
#define XPAR_OPB_PCI_1_PCI_PREFETCH_1                1
#define XPAR_OPB_PCI_1_PCI_SPACETYPE_1               1
#define XPAR_OPB_PCI_1_PCIBAR_2                      0x5F000000
#define XPAR_OPB_PCI_1_PCIBAR_LEN_2                  16
#define XPAR_OPB_PCI_1_PCIBAR2IPIF_2                 0x00000000
#define XPAR_OPB_PCI_1_PCIBAR_ENDIAN_TRANSLATE_EN_2  0
#define XPAR_OPB_PCI_1_PCI_PREFETCH_2                1
#define XPAR_OPB_PCI_1_PCI_SPACETYPE_2               1
#define XPAR_OPB_PCI_1_IPIFBAR_0                     0x80000000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_0               0x81FFFFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_0                 0xF0000000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_0 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_0               1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_0              1
#define XPAR_OPB_PCI_1_IPIFBAR_1                     0x82000000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_1               0x820007FF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_1                 0xCE000000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_1 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_1               1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_1              1
#define XPAR_OPB_PCI_1_IPIFBAR_2                     0x82320000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_2               0x8232FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_2                 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_2 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_2               1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_2              1
#define XPAR_OPB_PCI_1_IPIFBAR_3                     0x82330000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_3               0x8233FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_3                 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_3 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_3               1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_3              0
#define XPAR_OPB_PCI_1_IPIFBAR_4                     0x82340000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_4               0x8234FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_4                 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_4 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_4               0
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_4              0
#define XPAR_OPB_PCI_1_IPIFBAR_5                     0x82350000
#define XPAR_OPB_PCI_1_IPIF_HIGHADDR_5               0x8235FFFF
#define XPAR_OPB_PCI_1_IPIFBAR2PCI_5                 0x00010000
#define XPAR_OPB_PCI_1_IPIFBAR_ENDIAN_TRANSLATE_EN_5 0
#define XPAR_OPB_PCI_1_IPIF_PREFETCH_5               1
#define XPAR_OPB_PCI_1_IPIF_SPACETYPE_5              1
#define XPAR_OPB_PCI_1_DMA_BASEADDR                  0x87000000
#define XPAR_OPB_PCI_1_DMA_HIGHADDR                  0x8700007F
#define XPAR_OPB_PCI_1_DMA_CHAN_TYPE                 0
#define XPAR_OPB_PCI_1_DMA_LENGTH_WIDTH              11

/*****************************************************************************
 *
 * GEmac defines.
 * DeviceID starts at 210
 */
#define XPAR_XGEMAC_NUM_INSTANCES    1
#define XPAR_GEMAC_0_DEVICE_ID       210
#define XPAR_GEMAC_0_BASEADDR        0x61000000
#define XPAR_GEMAC_0_DMA_TYPE        9
#define XPAR_GEMAC_0_MIIM_EXIST      0
#define XPAR_GEMAC_0_INCLUDE_STATS   0


/*****************************************************************************
 *
 * Touchscreen defines .
 * DeviceID starts at 220
 */
#define XPAR_XTOUCHSCREEN_NUM_INSTANCES  1
#define XPAR_TOUCHSCREEN_0_DEVICE_ID     220
#define XPAR_TOUCHSCREEN_0_BASEADDR      0x70000000

/*****************************************************************************
 *
 * DDR defines .
 * DeviceID starts at 230
 */
#define XPAR_XDDR_NUM_INSTANCES         1
#define XPAR_DDR_0_DEVICE_ID            230
#define XPAR_DDR_0_BASEADDR             0
#define XPAR_DDR_0_INTERRUPT_PRESENT    0

/* xutil_memtest defines */

#define XUT_MEMTEST_INIT_VALUE  1

/** @name Memory subtests
 * @{
 */
/** See the detailed description of the subtests in the file description. */
#define XUT_ALLMEMTESTS     0
#define XUT_INCREMENT       1
#define XUT_WALKONES        2
#define XUT_WALKZEROS       3
#define XUT_INVERSEADDR     4
#define XUT_FIXEDPATTERN    5
#define XUT_MAXTEST         XUT_FIXEDPATTERN
/*@}*/

/***************** Macros (Inline Functions) Definitions *********************/


/************************** Function Prototypes ******************************/

/* xutil_memtest prototypes */

XStatus XUtil_MemoryTest32(Xuint32 *Addr, Xuint32 Words, Xuint32 Pattern,
                           Xuint8 Subtest);
XStatus XUtil_MemoryTest16(Xuint16 *Addr, Xuint32 Words, Xuint16 Pattern,
                           Xuint8 Subtest);
XStatus XUtil_MemoryTest8(Xuint8 *Addr, Xuint32 Words, Xuint8 Pattern,
                          Xuint8 Subtest);

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