- 博客(1)
- 资源 (10)
- 收藏
- 关注
转载 FPGA & Verilog开发经验若干
前些日子,因实验室的项目需要(不知如何将软件的逻辑转化成硬件逻辑),特请来院里一FPGA专家进行辅导,去旁听记下笔记若干并整理成文档,以免日后忘却。又,虽现在不做FPGA,但介绍的开发经验、思想方法等很难得,暂时记下,以备后用。1. wire与reg之外的数据类型不要在verilog代码中出现。2. assign(组合逻辑)与always之外的语句不要在verilog代码中出现。3. 一个module最好一个always,再加若干assign,这样便于控制。4.
2011-03-29 09:37:00 727
Serial Attached SCSI Standar
The information contained in this publication was gathered from many sources. Portions of the text used to
explain general SAS concepts were adapted in various forms, with permission, from the SCSI Trade Associa-tion, Hewett Packard Invent slides, and the T10/1760-D SAS-2 Interface Standard Draft 02.
2015-01-30
空空如也
TA创建的收藏夹 TA关注的收藏夹
TA关注的人