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Verilog testbench的写法之输入输出文件

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以下为代码和解释:


`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:03:48 08/31/2016
// Design Name:   Gaussian1
// Module Name:   D:/SIFT/project/SIFT_Gaussian/tb_Gaussian1.v
// Project Name:  SIFT_Gaussian
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Gaussian1
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_Gaussian1;

	// Inputs
	reg CLK;
	reg nRESET;
	reg [7:0] PIXEL_IN;
	reg VALID_IN;

	// Outputs
	wire VALID_OUT;
	wire [1214:0] DATA_OUT;
	
	reg [7:0] image_b [0:1023];  //输入文件大小
	integer read_addr;
	
	integer read_image_point;
	integer image_point;
	
	integer i;
	
	reg [14:0]data_buffer[0:575][0:80]  //输出文件大小
	integer data_cnt;
	integer data_cnt2;
	
	reg [18:0] write_addr;
	integer write_text_point;

	// Instantiate the Unit Under Test (UUT)
	Gaussian1 uut (
		.CLK(CLK), 
		.nRESET(nRESET), 
		.PIXEL_IN(PIXEL_IN), 
		.VALID_IN(VALID_IN), 
		.VALID_OUT(VALID_OUT), 
		.DATA_OUT(DATA_OUT)
	);

	initial begin
		// Initialize Inputs
		CLK = 0;
		nRESET = 0;
		PIXEL_IN = 0;
		VALID_IN = 0;
		
		read_addr = 0;
		read_image_point = $fopen("1.raw","rb+");  
		image_point = $fread(image_b,read_image_point);   // reg [7:0] image_b [0:1023]; 

		
		write_addr = 0;
		write_text_point = $fopen("normalization_result.txt"."wb+");
		
		data_cnt = 0;
		data_cnt2 = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		
		nRESET = 1;

	end
	
	initial begin
		forever begin
		#5 CLK = !CLK;
		end
	end
	
	always@(posedge CLK or negedge nRESET)
	begin
		if(!nRESET)
		begin	
			read_addr <= 0;
			PIXEL_IN <= 0;
		end
		
		else
		begin
			if(read_addr <= 1024)
			begin
				read_addr <= read_addr + 1;
				PIXEL_IN <= image_b[read_addr];    // reg [7:0] image_b [0:1023]; 
				VALID_IN <= 1'd1;
			end
		
			else
			begin
				VALID_IN <= 1'b0;
			end
		end
	end
	
	wire[14:0] divide_out_data[0:80];
	
	generate genvar i0;
		for(i0 = 0; i0 < 81; i0 = i0 + 1)
		begin : xxxxxxxxx
			assign divide_out_data[i0] = DATA_OUT[15*i0 + 14 : 15 * i0];    //wire [1214:0] DATA_OUT;
                                                                           DATA_OUT[(15*i0 + 14) : (15 * i0)] 15位  15*81 = 1215
		end
	endgenerate
	
	always@(posedge CLK or negedge nRESET)
	begin
		if(!nRESET)
		begin
			data_cnt2 <= 0;
		end
		
		else
		begin
			if(VALID_OUT == 1'd1)
			begin
				for(i=0; i<81; i = i + 1)
				begin
					data_buffer[data_cnt2][i] <= divided_out_data[i]];   
				end  
				data_cnt2 <= data_cnt2 + 1;
			end
		end
	end
	
	always@(posedge CLK or negedge nRESET)
	begin
		if(data_cnt2 == 576)
		begin
			for(n = 0; n < 576; n = n + 1)
			begin
				for(m = 0; m < 81; m = m + 1)
				begin
					$fwrite(write_text_point,data_buffer[n][m]);
					$fwrite(write_text_point, ",");
				end
			end
			
			$fclose(write_text_point);
		end
	end
	
	
      
endmodule



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