3.1. 键盘控制器 VHDL程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity key_controler is port ( clk : in std_logic;--时钟信号 cs : in std_logic;--片选信号 rd : in std_logic;--读信号 wr : in std_logic;--写信号 key_in : in std_logic_vector(7 downto 0);--键盘输入 int : out std_logic;--中断请求 data : out std_logic_vector(7 downto 0)--数据输出 ); end entity; architecture keyin of key_controler is signal key_0 : std_logic_vector(7 downto 0); signal key_1 : std_logic_vector(7 downto 0); signal key_2 : std_logic_vector(7 downto 0); signal key_3 : std_logic_vector(7 downto 0); signal key_4 : std_logic; signal clk_lock : std_logic; signal read_data : std_logic; signal int_clr : std_logic; begin process(clk)--去抖 begin if rising_edge(clk) then key_0<=key_in; key_1<=key_0; end if; end process; key_2<=(not key_1) and key_0;--键码脉冲 process(clk_lock,int_clr)--键码锁存,异步清除 begin if int_clr='0' then key_3<="00000000"; elsif falling_edge(clk_lock) then key_3<=key_2; end if; end process; key_4<=not (key_3(7) or key_3(6) or key_3(5) or key_3(4) or key_3(3) or key_3(2) or key_3(1) or key_3(0)); int<=key_4;--中断请求 clk_lock<=clk and key_4; read_data<=cs or rd;--读键码 data<=key_3 when read_data='0' else "ZZZZZZZZ";--三态门输出控制 int_clr<=cs or wr;--清除中断 end architecture; 3.2. 单片机读键码程序 #include #include unsigned char key_code; void display(char key_code) {……} void main(void) { IT0=1;//int0下降沿触发 EX0=1;//int0中断允许 EA=1;//开中断 4/5