EMBEDDED MICROPROCESSORS-Blackfin Processor Architecture Overview

转载 2013年12月04日 10:12:04

Blackfin Processors are a new breed of 16-32-bit embedded microprocessor designed specifically to meet the computational demands and power constraints of today's embedded audio, video and communications applications. Based on the Micro Signal Architecture (MSA) jointly developed with Intel Corporation, Blackfin Processors combine a 32-bit RISC-like instruction set and dual 16-bit multiply accumulate (MAC) signal processing functionality with the ease-of-use attributes found in general-purpose microcontrollers. This combination of processing attributes enables Blackfin Processors to perform equally well in both signal processing and control processing applications-in many cases deleting the requirement for separate heterogeneous processors. This capability greatly simplifies both the hardware and software design implementation tasks.

The Blackfin Processor family also offers industry leading power consumption performance down to 0.8V. This combination of high performance and low power is essential in meeting the needs of today's and future signal processing applications including broadband wireless, audio/video capable Internet appliances, and mobile communications.

All Blackfin Processors offer fundamental benefits to the system designer which include:

  • High-performance signal processing and efficient control processing capability enabling a variety of new markets and applications.
  • Dynamic Power Management (DPM) enabling the system designer to specifically tailor the device power consumption profile to the end system requirements.
  • Easy to use mixed 16-/32-bit Instruction Set Architecture and development tool suite ensuring that product development time is minimized.

High Performance Processor Core

The Blackfin Processor architecture is based upon a 10-stage RISC MCU/DSP pipeline with a mixed 16-/32-bit Instruction Set Architecture designed for optimal code density. Blackfin processors architecture is also fully SIMD compliant and includes instructions for accelerated video and image processing. The architecture is well suited for full signal processing / analytical capabilities while also offering efficient RISC MCU control tasking capabilities - on either a single or dual core device. With the optimal code density and the possibility of little to no code optimization, quicker time to market can be achieved without running into performance headroom barriers seen on other traditional processor.

High Bandwidth DMA Capability

All Blackfin Processors have multiple, independent DMA controllers that support automated data transfers with minimal overhead from the processor core. DMA transfers can occur between the internal memories and any of the many DMA-capable peripherals. Transfers can also occur between the peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller.

Video Instructions

In addition to native support for 8-bit data, the word size common to many pixel processing algorithms, the Blackfin Processor architecture includes instructions specifically defined to enhance performance in video processing applications. For example, Discrete Cosine Transform (DCT) is supported with an IEEE 1180 rounding operation, while the "SUM ABSOLUTE DIFFERENCE" instruction supports motion estimation algorithms used in video compression algorithms such as MPEG2, MPEG4, and JPEG.

Implementing video compression algorithms in software allows OEMs to adapt to evolving standards and new functional requirements without hardware changes. The enhanced instructions allow Blackfin Processors to be considered in applications previously addressed primarily by ASICs, VLIW media processors or hardwired chipsets. Ultimately, Blackfin Processors will help lower overall system cost while improving the time to market for the end application.

Efficient Control Processing

The Blackfin Processor architecture also offers a variety of benefits most often seen in RISC control processors. These features include a powerful and flexible hierarchical memory architecture, superior code density, and a variety of microcontroller-style peripherals including items such as 10/100 Ethernet MAC, UARTS, SPI, CAN controller, Timers with PWM support, Watchdog Timer, Real-Time Clock, and a glueless synchronous and asynchronous memory controller. All of these features provide the system designer with a great deal of design flexibility while minimizing end system costs.

Hierarchical Memory

The Blackfin Processor memory architecture provides for both Level 1 (L1) and Level 2 (L2) memory blocks in device implementations. The L1 memory is connected directly to the processor core, runs at full system clock speed, and offers maximum system performance for time critical algorithm segments. The L2 memory is a larger, bulk memory storage block that offers slightly reduced performance, but still faster than off-chip memory.

The L1 memory structure has been implemented to provide the performance needed for signal processing while offering the programming ease found in general purpose microcontrollers. This is accomplished by allowing the L1 memory to be configured as SRAM, cache, or a combination of both. By supporting both SRAM and cache programming models, system designers can allocate critical real time signal processing data sets that require high bandwidth and low latency into SRAM, while storing more 'soft' real time control / OS tasks in the cache memory.

Blackfin Processor memory architecture

The Memory Management Unit provides for a memory protection format that, when coupled with the core's User and Supervisor modes, can support a full Real Time Operating System. The RTOS runs in Supervisor mode and partitions blocks of memory and other system resources for the actual application software to run in User mode. Thus, the MMU offers an isolated and secure environment for robust systems and applications.

Superior Code Density

The Blackfin Processor architecture supports multi-length instruction encoding. Very frequently used control-type instructions are encoded as compact 16-bit words, with more mathematically intensive signal processing instructions encoded as 32-bit values. The processor will intermix and link 16-bit control instructions with 32-bit signal processing instructions into 64-bit groups to maximize memory packing. When caching and fetching instructions, the core automatically fully packs the length of the bus because it does not have alignment constraints. When combined, these two features enable Blackfin Processors to deliver code density benchmarks comparable to industry-leading RISC processors.

Dynamic Power Management

All Blackfin Processors employ multiple power saving techniques. Blackfin Processors are based on a gated clock core design that selectively powers down functional units on an instruction-by-instruction basis. Blackfin Processors also support multiple power-down modes for periods where little or no CPU activity is required. Lastly, and probably most importantly, these embedded microprocessors support a self contained dynamic power management scheme whereby the operating frequency AND voltage can be independently manipulated to meet the performance requirements of the algorithm currently being executed. These transitions may occur continually under the control of an RTOS or user firmware. Most Blackfin processors offer on-chip core voltage regulation circuitry as well as operation to as low as 0.8V and are particularly well suited for portable applications requiring extended battery life.

Easy to Use

A single Blackfin Processor can be utilized in many applications previously requiring both a high performance signal processor and a separate efficient control processor. This benefit greatly reduces development time and costs, ultimately enabling end products to get to market sooner. Additionally, a single set of development tools can be used, which decreases the system designer's initial expenses and learning curve.

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