FPGA test

原创 2012年03月29日 15:38:37

/*************************************************************************
 * Filename: fpga_test.c
 * Author:  Kung
 * Description: Test FPGA : 1.Test unchanged data;
 							2.Test randam data;
 							3.Test I/O;
 * Version: Formal
 * Date: 2012-03-29
 * History: none
 *************************************************************************/
 
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#include <errno.h>
#include <fcntl.h>
#include <termios.h>
#include <assert.h>
#include <unistd.h>
#include <sys/wait.h>
#include <sys/time.h>
#include <sys/ioctl.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
#include <arpa/inet.h>
#include <sys/socket.h>


#define		FPGA_VERSION_ADDR	0x7003
#define		INPUT_PORT_STATUE	0x7ffe
#define		OUTPUT_TEST_ADDR	0x0003	

#define		RANDAM_DATA_IN		0x0000    //test randam number
#define		RANDAM_DATA_OUT		0x7fff
#define		TEST_RANGE			0xffff

#define 	IO_DATA_IN 			0x0003
#define 	IO_DATA_OUT 		0x7ffe

#define  UNCHANGED_DATA_ADDR	0x7018		//store 4 unchanged-datas to four sequntial address. this is the first 													unchanged-data address at where you can read 0x1234. 
#define     UNCHANGED_DATA1		0x1234
#define		UNCHANGED_DATA2		0x5678
#define		UNCHANGED_DATA3		0x90ab
#define		UNCHANGED_DATA4		0xcdef

#define FPGA_INTERCON_ADDR 0X0001
#define FPGA_CONFIG_ADDR 0X0002

#define FPGA_INTERCON 0X0001
#define FPGA_CONFIG 0x007c

#define FPGA_CONFIG_ADDR_READ         0X7002
#define FPGA_INTERCONT_ADDR_READ     0X7004

void write_fpga(int fd,unsigned short address,unsigned short data)
{
	write(fd, &address, 1);	//write write-address
	write(fd, &data, 1);    //write data
}

void read_fpga(int fd,unsigned short address,unsigned short *data)
{
	write(fd, &address, 1);	//write read-address
	read(fd, data, 1);		//read data
}
 
int main(void)
{   
	int fpga_fd;
	unsigned int count = 0;
	unsigned int i,j;
	unsigned int test_unchagned_data_success_times = 0;
	unsigned int test_random_data_success_times = 0;
	unsigned int test_io_data_success_times = 0;
	unsigned int unchanged_data[4] = {UNCHANGED_DATA1, UNCHANGED_DATA2, UNCHANGED_DATA3, UNCHANGED_DATA4};
	unsigned short write_addr,read_addr;
	unsigned short  write_data, read_data = 0;
	char scan_buf[20];

    if ((fpga_fd = open("/dev/fpga0", O_RDWR)) < 0)    //open fpga
    {
        perror("Open fpga\n");
        exit(1);
    }
    
    usleep(100);

#if 1	//read fpga version
	read_addr = FPGA_VERSION_ADDR;
	read_fpga(fpga_fd, read_addr,&read_data);
	printf("FPGA version : %x\n", read_data);
#endif

#if 1	//test unchanged data
	read_data = 0;	
	printf("Read unchanged data");	
	for (i = 0; i < 4; ++i)
	{
		read_addr = UNCHANGED_DATA_ADDR + i;
		read_fpga(fpga_fd, read_addr,&read_data);
		if (read_data == unchanged_data[i])
		{
			test_unchagned_data_success_times++;
			printf("0x%x ", read_data);
		}
	} 
	printf("\n");
#endif

#if 1	//test random data
	write_addr = RANDAM_DATA_IN;
	read_addr = RANDAM_DATA_OUT;

	for (i = 0; i < 16; i++)
	{
		write_data = i<<i;
		
		write_fpga(fpga_fd, write_addr, write_data);				
		read_fpga(fpga_fd, read_addr,&read_data);

		if (write_data == read_data)
			test_random_data_success_times++;
//		else printf("FPGA & ARM data wire have problem at :  %2d\n",i);
	}
	
	for (i = 0; i < 16; i++)
	{
		write_data = ~(i<<i);
		
		write_fpga(fpga_fd, write_addr, write_data);				
		read_fpga(fpga_fd, read_addr,&read_data);

		if (write_data == read_data)
			test_random_data_success_times++;
//		else printf("FPGA & ARM data wire have problem at :  %2d\n",i);
	}
#endif

	//test IO data, configure the fpga before test IO
	for(i = 0; i < 3; i++) //set interrupt control information
	{
		write_addr = FPGA_INTERCON_ADDR;
		read_addr  = FPGA_INTERCONT_ADDR_READ;
		write_data = FPGA_INTERCON;
		
		write_fpga(fpga_fd,write_addr,write_data);
		read_fpga(fpga_fd,read_addr,&read_data);
//		printf("Read interrupt control configure : %d\n",read_data);
		if(read_data == FPGA_INTERCON)
			break;
		sleep(1);
	}
	if(3 == i)
		printf("FPGA EEROR : set interrupt control failed!\n");
	
	for(j = 0; j < 3; j++) //set FPGA configuration
	{
		write_addr = FPGA_CONFIG_ADDR;
		read_addr  = FPGA_CONFIG_ADDR_READ;
		write_data = FPGA_CONFIG;
		
		write_fpga(fpga_fd,write_addr,write_data);		
		read_fpga(fpga_fd,read_addr,&read_data);
//		printf("Read fpga system configre : %d\n",read_data);
		if(read_data == FPGA_CONFIG)
			break;
	}
	if(3 == j)
		printf("FPGA EEROR : set system control failed!\n");
	
	if (3 == i || 3 == j)	
		goto RESULT;

#if 1
	/* begin test IO port */
	write_addr = IO_DATA_IN;
	read_addr  = IO_DATA_OUT;
	printf("Please connect fpga output port wire!(ADDR0-4-->AD0-4)\n");
	printf("Are you ready ?(Y) : ");
	scanf("%s",scan_buf);
	while(strcasecmp(scan_buf,"y"))
	{
		printf("EEROR :invalid input!\n");
		scanf("%s",scan_buf);
	}

	for(i = 0; i < 5; i++)
	{
		write_data = 1<<i;
		write_fpga(fpga_fd,write_addr,write_data);
		read_fpga(fpga_fd,read_addr,&read_data);

		if(write_data == read_data)
		{
			test_io_data_success_times++;
			//printf("read_data = %d\n",read_data);
		}
		else
		{		
			printf("FPGA & AD WIRE have problem at AD%d--ADDR%d\n ",i,i);
			printf("write data is %d,read data is %d\n",write_data,read_data);
		}
	}

	for(i = 0; i < 5; i++)
	{
		write_data = (0x1f)&(~(1<<i));
		write_fpga(fpga_fd, write_addr, write_data);	
		read_fpga(fpga_fd, read_addr, &read_data);
		
		if(write_data == read_data)
			test_io_data_success_times++;
		else
		{		
			printf("FPGA & AD WIRE have problem at AD%d--ADDR%d\n ",i,i);
			printf("write data is %x,read data is %x\n",write_data,read_data);
		}
	}		
#endif		

	printf("\nPlease connect fpga output port wire!(ADDR0-4-->AD5-9)\n");
	printf("Are you ready ?(Y) : ");
	scanf("%s",scan_buf);
	while(strcasecmp(scan_buf,"y"))
	{
		printf("EEROR :invalid input!\n");
		scanf("%s",scan_buf);
	}

	for(i = 0;i < 5; i++)
	{
		write_data = 1<<i;
		write_fpga(fpga_fd, write_addr, write_data);	
		read_fpga(fpga_fd, read_addr, &read_data);
		
		switch(i)
		{
			case 0:
				write_data = 0x20;
				break;
			case 1:
				write_data = 0x40;
				break;
			case 2:
				write_data = 0x80;
				break;
			case 3:
				write_data = 0x100;
				break;
			case 4:
				write_data = 0x600;
				break;
			default:
				break;
		}
			
		if(write_data != read_data)
		{
			printf("FPGA & AD WIRE have problem in AD%d--ADDR%d\n ",i+5,i+5);
			printf("write data is %x,read data is %x\n",write_data,read_data);
		}
		else test_io_data_success_times++;
	}
	
	for(i = 0; i < 5; i++)
	{
		write_data = ~(1<<i);
		write_fpga(fpga_fd,write_addr,write_data);	
		read_fpga(fpga_fd,read_addr,&read_data);
		
		switch(i)
		{
			case 0:
				write_data = 0x7c0;
				break;
			case 1:
				write_data = 0x7a0;
				break;
			case 2:
				write_data = 0x760;
				break;
			case 3:
				write_data = 0x6e0;
				break;
			case 4:
				write_data = 0x1e0;
				break;
			default:
				break;
		}
		
		if(write_data != read_data)
		{
			printf("FPGA & AD WIRE have problem expect AD%d--ADDR%d\n ",i+5,i+5);
			printf("write data is %x,read data is %x\n",write_data,read_data);
		}
		else test_io_data_success_times++;
	}
	
RESULT:
#if 1	//test result
	printf("\n\nTest result :\n");
	count = 0;	
	if (4 == test_unchagned_data_success_times)
	{
		printf("Test unchanged data success!\n");
		count++;
	}
	else
		printf("Test unchanged data failed!\n");

	if (32 == test_random_data_success_times)
	{
		printf("Test random data success!\n");
		count++;
	}
	else
		printf("Test random data failed!\n");
		
	if (20 == test_io_data_success_times)
	{
		printf("Test IO port success!\n");
		count++;
	}
	else
		printf("Test IO port failed!\n");

	if (3 == count)
	{
		printf("**********************FPGA is OK!!*************************\n");
	}
	else
	printf("********************BAD FPGA************************\n");

	
#endif

     close(fpga_fd);

     return 0;
}

 


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