今天遇到的问题,记录下来。
· CPI 始终等于1。这显然是不正确的。 cycle和instruction以及CPI的计算都是由PK来完成的。
pk -s 中的 sys_exit
也就是说,pk中计算的CPI和cache模型中计算失效率是不想关的。
As you are debugging, please note that spike is not meant to be a cycle-accurate simulator of the assembly code. When spike runs, memory operations “magically” resolve in a single cycle, and branches are always evaluated without delay. The ISA simulator can evaluate the functional correctness of programs, but it is not a good way to measure how long they will take to run. Such cycle-accurate simulation requires a target hardware implementation such as the one that you will compile later in the lab. [1]
· cache的失效率的模拟
这个部分还没有深入去看,cache模型的模拟应该是有模型的。
· 关于cycle 的问题
在riscv 中,时钟的获取可以通过特殊的system指令 CSR系列来读取。
1. 伪代码方式 asm volatile ("rdcycle %0":"=r"(