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MMU with 16MB super sections

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MMU with 16MB super sections - howto?

 

Posted by Coolguy 11 July 2011 - 05:22 PM

Hi,

I am trying to setup MMU with 1:1 scheme (VA=PA). I wanted to try with a 16MB super section.

I first tried with 1MB section and created a 1:1 TLB with each entry being 1MB and it takes 16KB space with 4K entries. This works

Then i tried with 16MB super sections with only difference being - bit 18 set for each entry in the TLB. This is as per the ARM TRM.

Basically i am trying this during boot and hence i don't have 16KB free space to have 1MB TLB entry size. So i thought a 16MB entry will result in 256 entries => 1K space.

I am using ARM1176ej-s processor. When i searched i get this link "http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/CBACHHJG.html"

" Because each first level page table entry covers a 1MB region of virtual memory, the 16MB supersections require that 16 identical copies of the first level descriptor of the supersection exist in the first level page table."

I don't understand this line. Is the first level page table is always meant to be 16KB size? What is the benefit of 16MB super section then?

Can anyone post and example of having a 16MB supersection in TLB (256 entries) with 1:1 scheme?

Thanks.
 
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Posted by isogen74 11 July 2011 - 06:29 PM

Ok, first things first, lets correct some terminology as currently you are getting it wrong and it will only lead to confusion ...

The tables in memory which define the VA to PA translation are the translation tables, and each entry in the table is a "table descriptor".

The TLB is the "translation lookaside buffer" - effectively a cache of recent address translations so you don't keep having to perform conversions using the tables in main memory which are relatively slow.

引用

Is the first level page table is always meant to be 16KB size? What is the benefit of 16MB super section then?



Effectively yes (but not quite, more on that later). Super-sections have no impact on the L1 table size, so every entry in the L1 table covers 1MB of address space. For super sections you repeat the same entry 16 times.




Why bother - because you know all 16 items have the same address and access properties it means we only need one entry in the TLB cache to cover 16MB, rather than 1MB using normal sections. Therefore you can fit more address space translation ranges in your TLB at the same time; it goes faster.


引用

(but not quite, more on that later)



With the ARM1176 and the newer ARMv7A Cortex cores you can program the size for the L1 translation table. Each entry still covers 1MB but you can simply decide to expose less virtual address space to the applications - if you are happy with 512MB of virtual address space you only need to expose a 2KB L1 table, for example.

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