reg [1:0]cnt1;
reg div_clk;
always@(posedge clk or negedge rst)
if(!rst)begin
cnt1<=2'd0;
div_clk<=1'b1;
end
else if(cnt1<3)begin
cnt1<=cnt1+1'b1;
div_clk<=~div_clk;
end
else begin
cnt1<=2'b0;
div_clk<=1'b1;
end
reg [1:0]cnt1;
reg div_clk;
always@(posedge clk or negedge rst)
if(!rst)begin
cnt1<=2'd0;
div_clk<=1'b1;
end
else if(cnt1<3)begin
cnt1<=cnt1+1'b1;
div_clk<=~div_clk;
end
else begin
cnt1<=2'b0;
div_clk<=1'b1;
end