Verilog刷题-10-Wire_dec

题目描述

• 文字描述
  The circuits so far have been simple enough that the outputs are simple functions of the inputs. As circuits become more complex, you will need wires to connect internal components together. When you need to use a wire, you should declare it in the body of the module, somewhere before it is first used. (In the future, you will encounter more types of signals and variables that are also declared the same way, but for now, we’ll start with a signal of type wire).
  简单来说，就是进行wire类型变量的声明。
• 需要声明wire变量电路图示
  
• 对应的代码

  module top_module (
      input in,              // Declare an input wire named "in"
      output out             // Declare an output wire named "out"
  );
  
  wire not_in;           // Declare a wire named "not_in"
  
  assign out = ~not_in;  // Assign a value to out (create a NOT gate).
  assign not_in = ~in;   // Assign a value to not_in (create another NOT gate).
  endmodule   // End of module "top_module"
  

• 本次需要实现电路
  

代码

module top_module (
	input a,
	input b,
	input c,
	input d,
	output out,
	output out_n );
	
	wire w1, w2;		// Declare two wires (named w1 and w2)
	assign w1 = a&b;	// First AND gate
	assign w2 = c&d;	// Second AND gate
	assign out = w1|w2;	// OR gate: Feeds both 'out' and the NOT gate

	assign out_n = ~out;	// NOT gate
	
endmodule

参考代码：

module top_module (
	input a,
	input b,
	input c,
	input d,
	output out,
	output out_n );
	
	wire w1, w2;		// Declare two wires (named w1 and w2)
	assign w1 = a&b;	// First AND gate
	assign w2 = c&d;	// Second AND gate
	assign out = w1|w2;	// OR gate: Feeds both 'out' and the NOT gate

	assign out_n = ~out;	// NOT gate
	
endmodule

能使用较少资源就是用较少资源。

结果

题目网址

https://hdlbits.01xz.net/wiki/Wire_decl