# Verilog专题（二十一）经典水库题目

HDLBits网址：https://hdlbits.01xz.net/wiki/Main_Page

# 题目

Also include an active-high synchronous reset that resets the state machine to a state equivalent to if the water level had been low for a long time (no sensors asserted, and all four outputs asserted).

# Module Declaration

module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);

# 我的设计

感觉这道题目的信号理解好了，就能想出状态转移图。

状态数量：根据表格的状态转移，应该有四个状态分别代表不一样的水位。

状态根据输入转移：S1\S2\S3表示传感器，三个传感器都亮，表示水位到S3以上；S1和S2传感器亮，水位在S2-S3；只有S1传感器亮，水位在S1-S2；传感器都不亮，水位在S1之下；

输出：根据表格，可以看出这是一个Moore状态机，在below S1状态，FR1\2\3置1；在between S1 to S2状态，FR1\2置1,FR3置0；在between S2 to S3状态，FR1置1，FR2\3置0；在Above S3状态，都置0。

根据上面的分析，代码如下：

module top_module (    input clk,    input reset,    input [3:1] s,    output fr3,    output fr2,    output fr1,    output reg dfr);     parameter S0 = 1, S1 = 2, S2 = 4, S3 = 8;    reg [3:0] state, next_state;    // State transition logic    always@(*) begin            case(state)                S0: begin                    if(s[1] == 1 && s[2] == 0 && s[3] == 0)next_state = S1;                    else next_state = S0;                end                S1: begin                    if(s[1] == 1 && s[2] == 1 && s[3] == 0) next_state = S2;                    else if(s[1] == 1 && s[2] == 0 && s[3] == 0) next_state = S1;                    else next_state = S0;                end                S2: begin                    if(s[1] == 1 && s[2] == 1 && s[3] == 1) next_state = S3;                    else if(s[1] == 1 && s[2] == 0 && s[3] == 0) next_state = S1;                    else next_state = S2;                end                S3: begin                    if(s[1] == 1 && s[2] == 1 && s[3] == 1) next_state = S3;                    else next_state = S2;                 end          endcase    end​​    // State flip-flops with asynchronous reset    always@(posedge clk) begin        if(reset) state <= S0;        else state <= next_state;    end        // Output logic    //assign dfr = (state > next_state) ? 1 : 0;    reg state_lower;    always @(posedge clk)begin        if (reset || state < next_state)            state_lower <= 1'b0;        else if (state > next_state)            state_lower <= 1'b1;    end    assign dfr = (state == S0) || state_lower;            always@(*)begin        if(state == S0)begin            fr1=1;            fr2=1;            fr3=1;        end        else if(state == S1) begin            fr1=1;            fr2=1;            fr3=0;        end        else if(state == S2) begin            fr1=1;            fr2=0;            fr3=0;        end        else begin            fr1=0;            fr2=0;            fr3=0;         end    endendmodule​

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#### 对Verilog 初学者比较有用的整理(转自它处)

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