VHDL实现二进制转BCD码（8位二进制）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity BToD is--8二进制转3位BCD十进制,用大4加3法
    port (
        bin: in    STD_LOGIC_VECTOR (7 downto 0);--8位二进制输入，表示十进制数
        bai: out  STD_LOGIC_VECTOR (3 downto 0);--4位BCD输出，表示一个百位数
        ten: out  STD_LOGIC_VECTOR (3 downto 0);--4位BCD输出，表示一个十位数
        one: out STD_LOGIC_VECTOR (3 downto 0) --4位BCD输出，表示一个个位数     
    );
end BToD;
architecture bcd of BToD is
begin
  bcd1: process(bin)
  variable z: STD_LOGIC_VECTOR (19 downto 0);
  begin
    for i in 0 to 19 loop--i为LOOP的循环变量
  z(i) := '0';
    end loop;
  z(10 downto 3) := bin;
    for i in 0 to 4 loop
  if z(11 downto 8) > 4 then
    z(11 downto 8) := z(11 downto 8) + 3;
  end if;
  
  if z(15 downto 12) > 4 then
    z(15 downto 12) := z(15 downto 12) + 3;
  end if;
z(17 downto 1) := z(16 downto 0);
    end loop;
bai <= z(19 downto 16);
ten <= z(15 downto 12);
   one <= z(11 downto 8 );
  end process bcd1;            
end bcd;