HDLBits学习记录4-Verification&CS450-详细整理版~-CSDN博客

Verification: Reading Simulations

Finding bugs in code

Mux

module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output out  );

    // 错误：assign out = (~sel & a) | (sel & b);
    // 应改法1：
    /*    always @(*) begin
        if (sel)
            out=b;
        else 
            out=a;
    end */
    // 法2：
    assign out = sel?a:b;
   
endmodule

参考答案：

module top_module (
	input sel,
	input [7:0] a,
	input [7:0] b,
	output reg [7:0] out
);

	// 1. A mux coded as (~sel & a) | (sel & b) does not work for vectors.
	// This is because these are bitwise operators, and sel is only a 1 bit wide quantity,
	// which leaves the upper bits of a and b zeroed. It is possible to code it using
	// the replication operator, but this is somewhat difficult to read:
	//   ( {8{~sel}} & a ) | ( {8{sel}} & b )
	
	// 2. The simulation waveform shows that when sel = 1, a should be selected. This
	// is flipped in the suggested code.

    assign out = sel ? a : b;
	
endmodule

使用位运算符(~和&)来实现多路选择器是不适用于向量的，因为位运算符是逐位操作的，而sel只有一个比特。如果尝试将sel与向量a或b进行位与操作，由于sel只有一位，结果向量的高位将被置零，这不是我们想要的行为。注释中提到的使用复制运算符{8{~sel}}来扩展sel的值到8位，然后与a或b进行位与操作，虽然技术上可行，但代码可读性较差。

NAND

必须使用提供的门：

module andgate ( output out, input a, input b, input c, input d, input e );

module top_module (input a, input b, input c, output out);//

    //错误：andgate inst1 ( a, b, c, out );
	wire out_q;
    andgate inst(out_q,a,b,c,1'b1,1'b1);
    assign out=~out_q;
endmodule

Mux

错误：命名、sel给错

module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //

    wire mux0, mux1;
    mux2 mux0 ( sel[0],    a,    b, mux0 );
    mux2 mux1 ( sel[1],    c,    d, mux1 );
    mux2 mux2 ( sel[1], mux0, mux1,  out );

endmodule

改后：

module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //

    wire [7:0] mux0, mux1;
    mux2 mux01 ( sel[0],    a,    b, mux0 );
    mux2 mux11 ( sel[0],    c,    d, mux1 );
    mux2 mux21 ( sel[1], mux0, mux1,  out );

endmodule

Add/sub

错误：

module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output reg result_is_zero
);//

    always @(*) begin
        case (do_s