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翻译 VC Formal -- Introduction
Formal verification is complimentary to simulation-based verification,provides exhaustive analysis to ensure signoff quality verification
2023-10-24 17:12:42 627
芯片设计验证-Ieee standard for systemverilog
IEEE Standard for SystemVerilog是SystemVerilog语言的官方手册,适用于芯片行业的相关从业人员。
2023-10-24
AXI4 modifiable transaction
2024-02-29
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