PYNQ-Z1 资源分析

学习记录

概述

核心：XC7Z020-1CLG400C（速度等级为-1，数字越大越好）
存储器：512MB DDR3，16MB Quad-SPI Flash

架构

ARM Cortex-A9处理系统和集成的现场可编程门阵列FPGA架构

PS部分

PL部分

编程模式

SD：引导镜像
QSPI：实现程序掉电不丢失
JTAG：FPGA开发或嵌入式开发

Basic I/O

Two tri-color LEDs, 2 switches, 4 push buttons, and 4 individual LEDs are connected to the Zynq PL
按键默认状态为低电平

To light up the tri-color LED, the corresponding signals need to be driven high. Ensuring that none of the tri-color signals are driven with more than a 50% duty cycle.

PMOD

Pmod ports are 2×6, right-angle, 100-mil spaced female connectors
The VCC and Ground pins can deliver up to 1A of current
both of Pmod ports are the high-speed type.

clock

The PYNQ-Z1 provides a 50 MHz clock to the Zynq PS_CLK input
The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and
the DDR3 memory controller to operate at a maximum of 525 MHz (1050 Mbps)
Additionally, the PYNQ-Z1 provides an external
125 MHz reference clock directly to pin H16 of the PL

复位资源

1. 上电复位POR
2. PL复位
   button PROG
   
3. 处理器子系统复位
   PS复位（PL也复位）不会重新采样引导模式
   button SRST
   

参考文献

1. PYNQ-Z1 Board Reference Manual

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