Fsm onehot 答题记录_output 'sum' has 999 mismatches. first mismatch oc-CSDN博客

本文链接：https://blog.csdn.net/I_LOVE_MCU/article/details/125985770

该博客探讨了在Verilog中设计有限状态机（FSM）时，针对错误输入处理的三种不同策略：将所有错误归入空闲状态，设置有优先级的错误处理以及无优先级的独热码处理。每种策略通过示例代码展示，并通过错误匹配数量来评估其效果。优化后的FSM在输出匹配性和资源利用率方面有所提升。

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Source:https://hdlbits.01xz.net/wiki/Fsm_onehot
题目没啥问题，只是没有描述清楚要求。
在一遍遍的提交过程中逐渐明晰
可以看ifdef的三种情况

// nodefine
// 错误输入全部归入idle
// # Hint: Output 'next_state' has 1157 mismatches. First mismatch occurred at time 1120.
// # Hint: Output 'out1' has 724 mismatches. First mismatch occurred at time 1120.
// # Hint: Output 'out2' has 744 mismatches. First mismatch occurred at time 1120.
// # Hint: Total mismatched samples is 1157 out of 1422 samples

// `define CUSTOM
// 有优先级的错误输入，低位优先级更高，具有排他性
// # Hint: Output 'next_state' has 922 mismatches. First mismatch occurred at time 1125.
// # Hint: Output 'out1' has no mismatches.
// # Hint: Output 'out2' has no mismatches.
// # Hint: Total mismatched samples is 922 out of 1422 samples

`define FINAL
// 没有优先级的独热码，可以兼容多个热码

三种不同的尝试

module top_module(
	// input clk,
    input in,
	// input rst_n,
    input  [9:0] state,
    output [9:0] next_state,
    output out1,
    output out2);
    
	localparam 	s0 = 10'b0000_0001,
				s1 = 10'b0000_0010,
				s2 = 10'b0000_0100,
				s3 = 10'b0000_1000,
				s4 = 10'b0001_0000,
				s5 = 10'b0010_0000,
				s6 = 10'b0100_0000,
				s7 = 10'b1000_0000,
				s8 = 10'b1_0000_0000,
				s9 = 10'b10_0000_0000,
				idle = 10'b0;
	
	// nodefine
	// 错误输入全部归入idle
	// # Hint: Output 'next_state' has 1157 mismatches. First mismatch occurred at time 1120.
	// # Hint: Output 'out1' has 724 mismatches. First mismatch occurred at time 1120.
	// # Hint: Output 'out2' has 744 mismatches. First mismatch occurred at time 1120.
	// # Hint: Total mismatched samples is 1157 out of 1422 samples

	// `define CUSTOM
	// 有优先级的错误输入，低位优先级更高，具有排他性
	// # Hint: Output 'next_state' has 922 mismatches. First mismatch occurred at time 1125.
	// # Hint: Output 'out1' has no mismatches.
	// # Hint: Output 'out2' has no mismatches.
	// # Hint: Total mismatched samples is 922 out of 1422 samples

	`define FINAL
	// 没有优先级的独热码，可以兼容多个热码
	
	`ifdef CUSTOM
		always@(*)begin
			casez(state)
				10'bzz_zzzz_zzz1:next_state = in? s1:s0;
				10'bzz_zzzz_zz10:next_state = in? s2:s0;
				10'bzz_zzzz_z100:next_state = in? s3:s0;
				10'bzz_zzzz_1000:next_state = in? s4:s0;
				10'bzz_zzz1_0000:next_state = in? s5:s0;
				10'bzz_zz10_0000:next_state = in? s6:s8;
				10'bzz_z100_0000:next_state = in? s7:s9;
				10'bzz_1000_0000:next_state = in? s7:s0;
				10'bz1_0000_0000:next_state = in? s1:s0;
				10'b10_0000_0000:next_state = in? s1:s0;
				default:next_state = idle;
			endcase
		end
	`elsif FINAL
		assign next_state[0] = ~in && (state[0]|state[1]|state[2]|state[3]|state[4]|state[7]|state[8]|state[9]) ;
		assign next_state[1] = in && (state[8]|state[9]|state[0]);
		assign next_state[2] = in && state[1];
		assign next_state[3] = in && state[2];
		assign next_state[4] = in && state[3];
		assign next_state[5] = in && state[4];
		assign next_state[6] = in && state[5];
		assign next_state[7] = in && (state[6]|state[7]) ;
		assign next_state[8] = ~in && state[5] ;
		assign next_state[9] = ~in && state[6] ;
	`else
		always @(*) begin
			case (state)
				s0:
					if(in)
						next_state <= s1;
					else
						next_state <= s0;
				s1:
					if(in)
						next_state <= s2;
					else
						next_state <= s0;
				s2:
					if(in)
						next_state <= s3;
					else
						next_state <= s0;
				s3:
					if(in)
						next_state <= s4;
					else
						next_state <= s0;
				s4:
					if(in)
						next_state <= s5;
					else
						next_state <= s0;
				s5:
					if(in)
						next_state <= s6;
					else
						next_state <= s8;
				s6:
					if(in)
						next_state <= s7;
					else
						next_state <= s9;
				s7:
					if(in)
						next_state <= s7;
					else
						next_state <= s0;
				s8:
					if(in)
						next_state <= s1;
					else
						next_state <= s0;
				s9:
					if(in)
						next_state <= s1;
					else
						next_state <= s0;
				
				default: 
					next_state <= idle;
			endcase
		end
	`endif

	// assign next_state = next_state;

`ifdef CUSTOM
	assign out1 = state[8] | state[9];
    assign out2 = state[7] | state[9];
`elsif FINAL
	assign out1 = state[8] | state[9];
    assign out2 = state[7] | state[9];
`else
	assign out1 = (state == s8 || state == s9);

	assign out2 = (state == s9 || state == s7);

`endif

endmodule

Reference