FPGA——表决器

描述 “表决器” 的VHDL程序

library ieee;
use ieee.std_logic_1164.all;

entity b7 is 
	port (a:in std_logic_vector(6 downto 0) ;
			b:out std_logic);
end b7;

architecture bhv of b7 is
begin 
	process (a)
	variable Q:integer;
	begin
		Q:=0;
		for n in 0 to 6 loop
		if (a(n)='1')then 
			Q:=Q+1;
		end if;
		end loop;
		if Q>4 then
			b <= '1';
		else b <= '0';
		end if;
	end process;
end bhv;