Countbcd_HDLbits(计数器)

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module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);
    
    assign ena[1] = (q[3:0] ==4'b1001)? 1:0;
    assign ena[2] = ((q[7:4] ==4'b1001)&&(ena[1]))? 1:0;
    assign ena[3] =( (q[11:8] ==4'b1001)&&(ena[2]))? 1:0;
     
	one_decade i1(clk,reset,1,q[3:0]);
    one_decade i2(clk,reset,ena[1],q[7:4]);
    one_decade i3(clk,reset,ena[2],q[11:8]);
    one_decade i4(clk,reset,ena[3],q[15:12]);

endmodule

module one_decade(input clk,input reset,input enable,output [3:0] q);
    always @(posedge clk)
        begin
        if(reset) q<=0;
            else if(enable) 
                begin 
 					 if(q==4'b1001 ) q<=0;
                    	else q<=q+1;
           	    end
        end
endmodule

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