FPGA：参数化的VGA控制器，可用于DVI/HDMI。

NoNoUnknow

已于 2023-09-19 17:59:07 修改

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分类专栏： FPGA学习文章标签： fpga开发

于 2023-08-06 21:51:11 首次发布

本文链接：https://blog.csdn.net/NoNoUnknow/article/details/132136035

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进行了参数化的VGA/DVI控制器，想改什么时序改动参数就可以，TFT和普通LCD屏也可以用。

#(
    parameter   H_Sync       = 96,
    parameter   H_backporch  = 40 ,
    parameter   H_left       = 8  ,
    parameter   H_data       = 640,
    parameter   H_right      = 8  ,
    parameter   H_Frontporch = 8  ,
    parameter   H_total      = H_Sync + H_backporch + H_left + H_data + H_right + H_Frontporch,
    parameter   H_width      = $clog2(H_total),
    parameter   V_Sync       = 2,
    parameter   V_backporch  = 25 ,
    parameter   V_left       = 8  ,
    parameter   V_data       = 480,
    parameter   V_right      = 8  ,
    parameter   V_Frontporch = 2  ,
    parameter   V_total      = V_Sync + V_backporch + V_left + V_data + V_right + V_Frontporch,
    parameter   V_width      = $clog2(V_total),
    // parameter   RGB_width    = 24,
    parameter   window       = 200
)

因为有需求所以，嵌入了一个白块自由移动，不需要的话删掉就可以。

主要思想就是通过两个计数器分别计算行和列的像素，然后利用计数器来改动开窗（白块）的位置，希望传入自己的图片也可以对其进行适当修改。

//
    always@(posedge Sys_clk or negedge Rst_n) begin
        if(Rst_n == 0) begin
            x_move <= 0;
        end else if((H_cnt_move ==  H_data - 1'b1 -window)
                 && (V_cnt == V_total - 1'b1) 
                 && (H_cnt == H_total - 1'b1)) begin
            x_move <= 1;
        end else if((H_cnt_move ==  1)
                && (V_cnt == V_total - 1'b1) 
                && (H_cnt == H_total - 1'b1)) begin
            x_move <= 0;
        end else begin
            x_move <= x_move;
        end
    end
    always@(posedge Sys_clk or negedge Rst_n) begin
        if(Rst_n == 0) begin
            y_move <= 0;
        end else if((V_cnt_move == V_data - 1'b1 - window)
                 && (V_cnt == V_total - 1'b1) 
                 && (H_cnt == H_total - 1'b1)) begin
            y_move <= 1;
        end else if((V_cnt_move ==  1)
                 && (V_cnt == V_total - 1'b1) 
                 && (H_cnt == H_total - 1'b1)) begin
            y_move <= 0;
        end else begin
            y_move <= y_move;
        end
    end
    always@(posedge Sys_clk or negedge Rst_n) begin
        if (Rst_n == 0) begin
            H_cnt_move <= 0;
        end else if(V_full && x_move == 0) begin
            H_cnt_move <= H_cnt_move + 1'b1;
        end else if(V_full && x_move == 1) begin
             H_cnt_move <= H_cnt_move - 1'b1;
        end else begin
            H_cnt_move <= H_cnt_move;
        end
    end 
    always@(posedge Sys_clk or negedge Rst_n) begin
        if (Rst_n == 0) begin
            V_cnt_move <= 0;
        end else if(V_full && y_move == 1) begin
            V_cnt_move <= V_cnt_move - 1;
        end else if(V_full && y_move == 0) begin
            V_cnt_move <= V_cnt_move + 1;
        end else begin
            V_cnt_move <= V_cnt_move;
        end
    end 
    always@(posedge Sys_clk or negedge Rst_n) begin
        if(Rst_n == 0) begin
            set_sign <= 0;
        end else if(Pixl_avai) begin
            if((H_addr <= H_cnt_move + window -1'b1) 
            && (H_addr >= H_cnt_move) 
            && (V_addr <= V_cnt_move + window -1'b1) 
            && (V_addr >= V_cnt_move))  begin
                set_sign <= 1'b1;
            end else begin
                set_sign <= 0;
            end
        end else begin
            set_sign <= 0;
        end
    end
    always@(posedge Sys_clk or negedge Rst_n) begin
        if(Rst_n == 0) begin
            rgb <= black;
        end else if(set_sign) begin
            rgb <= white;
        end else begin
            rgb <= black;
        end
    end
///

完整代码：

module vga_ctrl #(
    parameter   H_Sync       = 96,
    parameter   H_backporch  = 40 ,
    parameter   H_left       = 8  ,
    parameter   H_data       = 640,
    parameter   H_right      = 8  ,
    parameter   H_Frontporch = 8  ,
    parameter   H_total      = H_Sync + H_backporch + H_left + H_data + H_right + H_Frontporch,
    parameter   H_width      = $clog2(H_total),
    parameter   V_Sync       = 2,
    parameter   V_backporch  = 25 ,
    parameter   V_left       = 8  ,
    parameter   V_data       = 480,
    parameter   V_right      = 8  ,
    parameter   V_Frontporch = 2  ,
    parameter   V_total      = V_Sync + V_backporch + V_left + V_data + V_right + V_Frontporch,
    parameter   V_width      = $clog2(V_total),
    // parameter   RGB_width    = 24,
    parameter   window       = 200
)(
    input   wire            Sys_clk     ,
    input   wire            Rst_n       ,
    // input   wire    [RGB_width-1:0]   RGB_IN      , 
    output  wire    [2:0]   red_sign    ,
    output  wire    [2:0]   grenn_sign  ,
    output  wire    [1:0]   blue_sign   ,
    output  reg             H_Sync_sign ,
    output  reg             V_Sync_sign ,
    output  wire    [H_width-1:0] H_addr,
    output  wire    [V_width-1:0] V_addr
);
    localparam white = 8'b111_111_11;
    localparam black = 8'b000_000_00;
            // reg     [23:0]          reg_RGB;
            reg     [7:0]           rgb;
            reg     [H_width-1:0]   H_cnt ;
            reg     [H_width-1:0]   H_cnt_move ;
            reg                     H_full;
            reg     [V_width-1:0]   V_cnt ;
            reg     [V_width-1:0]   V_cnt_move ;
            reg                     V_full;
           wire                     Pixl_avai;
            reg                     set_sign ;
            reg                     x_move;//移动标志位x_axis
            reg                     y_move;//移动标志位y_axis
    assign H_addr    =  (Pixl_avai)?(H_cnt - (H_Sync + H_backporch +  H_left)):0;
    assign V_addr    =  (Pixl_avai)?(V_cnt - (V_Sync + V_backporch +  V_left)):0;
    assign Pixl_avai = (H_cnt >  (H_Sync + H_backporch  + H_left  -1'b1 ))
                    && (H_cnt <= (H_total- H_Frontporch - H_right -1'b1 )) 
                    && (V_cnt >  (V_Sync + V_backporch +  V_left  -1'b1 ))
                    && (V_cnt <= (V_total- V_Frontporch - V_right -1'b1 ));
    assign {red_sign,grenn_sign,blue_sign} = (Pixl_avai) ? rgb : 8'd0;
    always@(posedge Sys_clk or negedge Rst_n) begin
        if(Rst_n == 0) begin
            H_Sync_sign <= 1'b1;
        end else if(H_cnt == H_total - 1'b1) begin
            H_Sync_sign <= 1'b1;
        end else if(H_cnt == H_Sync -1'b1) begin
            H_Sync_sign <= 1'b0;
        end
    end
    always@(posedge Sys_clk or negedge Rst_n) begin
        if(Rst_n == 0) begin
            V_Sync_sign <= 1'b1;
        end else if((V_cnt == V_total - 1'b1) && (H_cnt == H_total - 1'b1)) begin
            V_Sync_sign <= 1'b1;
        end else if((V_cnt == V_Sync  - 1'b1) && (H_cnt == H_total - 1'b1)) begin
            V_Sync_sign <= 1'b0;
        end
    end
    // always@(posedge Sys_clk or negedge Rst_n) begin
    //     if(Rst_n == 0) begin
    //         reg_RGB <= 0;
    //     end else begin
    //         reg_RGB <= RGB_IN;
    //     end
    // end
//
    always@(posedge Sys_clk or negedge Rst_n) begin
        if(Rst_n == 0) begin
            x_move <= 0;
        end else if((H_cnt_move ==  H_data - 1'b1 -window)
                 && (V_cnt == V_total - 1'b1) 
                 && (H_cnt == H_total - 1'b1)) begin
            x_move <= 1;
        end else if((H_cnt_move ==  1)
                && (V_cnt == V_total - 1'b1) 
                && (H_cnt == H_total - 1'b1)) begin
            x_move <= 0;
        end else begin
            x_move <= x_move;
        end
    end
    always@(posedge Sys_clk or negedge Rst_n) begin
        if(Rst_n == 0) begin
            y_move <= 0;
        end else if((V_cnt_move == V_data - 1'b1 - window)
                 && (V_cnt == V_total - 1'b1) 
                 && (H_cnt == H_total - 1'b1)) begin
            y_move <= 1;
        end else if((V_cnt_move ==  1)
                 && (V_cnt == V_total - 1'b1) 
                 && (H_cnt == H_total - 1'b1)) begin
            y_move <= 0;
        end else begin
            y_move <= y_move;
        end
    end
    always@(posedge Sys_clk or negedge Rst_n) begin
        if (Rst_n == 0) begin
            H_cnt_move <= 0;
        end else if(V_full && x_move == 0) begin
            H_cnt_move <= H_cnt_move + 1'b1;
        end else if(V_full && x_move == 1) begin
             H_cnt_move <= H_cnt_move - 1'b1;
        end else begin
            H_cnt_move <= H_cnt_move;
        end
    end 
    always@(posedge Sys_clk or negedge Rst_n) begin
        if (Rst_n == 0) begin
            V_cnt_move <= 0;
        end else if(V_full && y_move == 1) begin
            V_cnt_move <= V_cnt_move - 1;
        end else if(V_full && y_move == 0) begin
            V_cnt_move <= V_cnt_move + 1;
        end else begin
            V_cnt_move <= V_cnt_move;
        end
    end 
    always@(posedge Sys_clk or negedge Rst_n) begin
        if(Rst_n == 0) begin
            set_sign <= 0;
        end else if(Pixl_avai) begin
            if((H_addr <= H_cnt_move + window -1'b1) 
            && (H_addr >= H_cnt_move) 
            && (V_addr <= V_cnt_move + window -1'b1) 
            && (V_addr >= V_cnt_move))  begin
                set_sign <= 1'b1;
            end else begin
                set_sign <= 0;
            end
        end else begin
            set_sign <= 0;
        end
    end
    always@(posedge Sys_clk or negedge Rst_n) begin
        if(Rst_n == 0) begin
            rgb <= black;
        end else if(set_sign) begin
            rgb <= white;
        end else begin
            rgb <= black;
        end
    end
///
    always@(posedge Sys_clk or negedge Rst_n) begin
        if(Rst_n == 0) begin
            H_cnt <= 0;
        end else if(H_cnt == H_total - 1'b1) begin
            H_cnt <= 0;
        end else begin
            H_cnt <= H_cnt + 1'b1;
        end
    end
    always@(posedge Sys_clk or negedge Rst_n) begin
        if(Rst_n == 0) begin
            H_full <= 1'b0;
        end else if(H_cnt == H_total - 1'b1) begin
            H_full <= 1'b1;
        end else begin
            H_full <= 1'b0;
        end
    end
    always@(posedge Sys_clk or negedge Rst_n) begin
        if(Rst_n == 0) begin
            V_cnt <= 0;
        end else if((V_cnt == V_total - 1'b1) && (H_cnt == H_total - 1'b1)) begin
            V_cnt <= 0;
        end else if(H_cnt == H_total - 1'b1) begin
            V_cnt <= V_cnt + 1'b1;
        end else begin
            V_cnt <= V_cnt;
        end
    end
    always@(posedge Sys_clk or negedge Rst_n) begin
        if(Rst_n == 0) begin
            V_full <= 1'b0;
        end else if((V_cnt == V_total - 1'b1) && (H_cnt == H_total - 1'b1)) begin
            V_full <= 1'b1;
        end else begin
            V_full <= 1'b0;
        end
    end
endmodule

显示情况：VGA-CSDN直播