Advanced Computer Architeture
RizeJin
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Interleaved memory
<br />One way of allocating virtual addresses to memory modules is to divide the memory space into contiguous blocks. The CPU can access alternate sections immediately, without waiting for memory to catch up (through wait states). Interleaved memory is one转载 2010-09-13 10:18:00 · 4618 阅读 · 0 评论 -
OProfile on Ubuntu 10.10 (OCT. 13, 2010)
moss@moss-PC:/usr/src/linux-headers-2.6.35-22$ sudo apt-get install oprofileReading package lists... DoneBuilding dependency tree Reading state information... DoneThe following extra packages will be installed: libopagent1Suggested pac原创 2010-10-13 21:57:00 · 1601 阅读 · 0 评论 -
Amdahl’s law (阿姆达尔定律)的演化和思考
from: http://manio.org/progress-and-thoughts-of-amdahls-law-286.htmlG.M.Amdahl在1967年提出了Amdahl’s law,针对并行处理的scalability给出了一个模型,指出使用并行处理的提速由问题的可并行的部分所决定。这个模型为并行计算系统的设计者提供了指导。其形式如下:f为问题中可被并行处理的部分的比例,m为并行处理机的数量,Speedup为并行后相比串行时的提速。Amdahl’s law表明在问题的可并行部分不大时,增加转载 2010-10-03 00:01:00 · 2303 阅读 · 0 评论 -
Hardwired control versus
<br />Hardwired control is a control mechanism to generate control signals by using appropriate finite state machine (FSM). Microprogrammed control is a control mechanism to generate control signals by using a memory called control storage (CS), which cont原创 2010-10-05 15:49:00 · 747 阅读 · 0 评论 -
Cache coherent NUMA (ccNUMA)
FORM: http://en.wikipedia.org/wiki/Cache_coherenceIn computing, cache coherence (also cache coherency) refers to the consistency of data stored in local caches of a shared resource. Cache coherence is a special case of memory coherence.When clients in a sy转载 2010-09-07 15:46:00 · 1664 阅读 · 0 评论 -
Effective Access Time
A paging scheme uses a Translation Loo-aside Buffer (TLB) A TLB access takes 10 ns and a main memory access takes 50 ns. What is the effective access time (in ns) if the TLB hit ratio is 90% and there is no page-fault?a) 54b) 60c) 65d) 75Dear student,the c原创 2010-09-16 22:12:00 · 1951 阅读 · 0 评论 -
K-ary N-cube
N = dimension K = number of nodes on each edge e.g., 4-ary 2-cube is a 4x4 2D mesh Hypercube is a 2-ary N-cube Has been shown that larger K and smaller N is more effective, scalable, easier to build原创 2010-09-07 20:33:00 · 1209 阅读 · 0 评论 -
对剖宽度
<br />from: http://zh.wikipedia.org/zh-sg/%E5%AF%B9%E5%89%96%E5%AE%BD%E5%BA%A6#<br /> <br />网络的对剖宽度(Bisection Width)是指对分网络所要移去的最少边数。 其数目等于对剖平面的链路数,与每条链路的连线数(或称作链路宽度或通道宽度)二者之间的乘积,即表示穿越对剖平面总共的连线数。原创 2010-09-07 20:15:00 · 2667 阅读 · 0 评论 -
Reservation Table Analyzer
Reservation Table Analyzerhttp://www.ecs.umass.edu/ece/koren/architecture/ResTable/SimpRes/原创 2010-09-16 13:49:00 · 884 阅读 · 0 评论 -
Cache Mapping and Associativity
A very important factor in determining the effectiveness of the level 2 cache relates to how the cache is mapped to the system memory. What this means in brief is that there are many different ways to allocate the storage in our cache to the memory address转载 2010-09-14 13:45:00 · 1075 阅读 · 0 评论 -
Superscalar
• A superscalar architecture is one in which several instructions can be initiated simultaneously and executed independently.• Pipelining allows several instructions to be executed at the same time, but they have to be in different pipeline stages at a giv原创 2010-09-15 19:10:00 · 754 阅读 · 0 评论 -
how to solve aliasing problem
Aliasing causes a substantial problem because it is often difficult or impossible to decide what objects a pointer may refer to. A compiler must be conservative; some compilers will not allocate any local variables of a procedure in a register when there i原创 2010-09-14 12:43:00 · 1071 阅读 · 0 评论 -
递归和迭代
<br />作者:拒绝潜水的鱼出处:http://slave2.cnblogs.com/ 归与迭代都是基于控制结构:迭代用重复结构,而递归用选择结构。递归与迭代都涉及重复:迭代显式使用重复结构,而递归通过重复函数调用实现重复。递归与迭代都涉及终止测试:迭代在循环条件失败时终止,递归在遇到基本情况时终止。使用计数器控制重复的迭代和递归都逐渐到达终止点:迭代一直修改计数器,直到计数器值使循环条件失败;递归不断产生最初问题的简化副本,直到达到基本情况。迭代和递归过程都可以无限进行:如果循环条件测试永远不变成fal转载 2011-01-10 16:53:00 · 1365 阅读 · 0 评论