美光 DDR4 的Feature 列表
8n-bit prefecth
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit
wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit
- wide, one-half-clock-cycle data transfers at the I/O pins.
Precharge
precharge的目的是在关闭row之前,将sense amplifer中存储的row最新值回刷到对应存储空间中。
有两种precharge方式:auto precharge 、 not auto precharge
- 在read/write cmd中,由A10来指示是否auto precharge .
- A10= 1 , 则在read/write cmd之后,auto precharge, 不需要DDRC额外发出precharge cmd。此时,只会对read/write对应的bank进行precharge。
- A10= 0,则read/write cmd之后,not auto precharge。需要DDRC额外发出precharge cmd 。
- precharge cmd 对应的A10 determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH)
Refresh
DDR4 要求:All banks of the SDRAM must be pre charged and idle for a minimum of the precharge time, tRP (MIN), before the REFRESH command can be applied.
每次refresh的地址是有DDR内部的refresh controller 生成,外部不可控。
两个时序控制参数:
- tRFC:refresh cmd -->next valid cmd 的最小时间,和DDR的容量是相关的;
- tREFI:refresh cmd -->next refresh cmd的间隔时间
refresh 受温度影响:
Self Refresh
self refresh 是在周边系统power-down的状态,维持存储空间的数据不变(有点低功耗的味道)。进入self refresh后,通过built-in timer来执行refresh,不再需要外部的ck输入,而且此时除了cke和reset_n信号外,其他信号均为don't-care.
write leveling
参考链接:DDR 学习时间 (Part B - 3):Write Leveling - 知乎
ACTIVATE Command
- 同一个bank只能有一个row是激活状态,在激活相同bank的其他row之前,需要对当前row进行precharge。
- activate cmd有3个时序约束:
- tRRD_S:不同BG的act cmd间隔;
- tRRD_L:相同BG的act cmd间隔;
- tFAW:连续4个act cmd 后,fifth act cmd 相对first act cmd的间隔。
Timing 参数汇总
tRRD_S | ACTIVATE-to-ACTIVATE command period (short); applies to consecutive ACTI VATE commands to different bank groups | |
tRRD_L | ACTIVATE-to-ACTIVATE command period (long); applies to consecutive ACTIVATE commands to the different banks in the same bank group | |
tWTR_S | 相同BG,写->读命令的间隔,从最后一拍写数据的下一个上升沿开始计算。 | 2 * CK |
tWTR_L | 不同BG,写->读命令的间隔,从最后一拍写数据的下一个上升沿开始计算。 | 4 * CK |
tDQSCK | the actual position of a rising strobe edge relative to CK | |
CL | CAS Latency,CAS读命令信号激活后到第一位数据输出的潜伏周期,潜伏周期是为了提高系统稳定性存在的 | RL=CL+AL |
AL | CAS Additive Latency,读/写命令激活的潜伏期,该潜伏用以保证数据读/写的可持续带宽。 | |
tRCD | RAS-CAS delay,行寻址至列寻址延迟时间,这个延时是为了满足命令激活到读/写命令的切换 | |
CWL | CAS Write Latency ,CAS写命令信号激活后到第一位数据输入的潜伏周期(类似CL) | WL=AL+CAL |
tRTP | the internal READ command to PRECHARGE command delay. tRTP (MIN) = MAX (4 × nCK, 7.5ns) | |
tRP | All banks of the SDRAM must be precharged and idle for a minimum of the precharge time, tRP (MIN), before the REFRESH command can be applied. | |
tWR | tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank | 12 * CK |
tRFC | A delay between the REFRESH command and the next valid command, except DES, must be greater than or equal to the minimum REFRESH cycle time tRFC.(refresh所需的时间) | The tRFC timing parameter depends on memory density |
tREFI | In general, a REFRESH command needs to be issued to the device regularly every tREFI interval.(refresh 命令的间隔时间) | |
参考:
聊一聊DDR(4)- 鱼的记忆 之 refresh - 知乎
DDR PHY的技术门槛 - 知乎
DDR4技术原理详解_ddr4 协议_ctbinzi的博客-CSDN博客
DRAM知识整理系列(三):部分时序参数整理_read command to 1st data out timing_不吃鱼的猫丿的博客-CSDN博客
DDR4相对于DDR3提升了速率,主要是通过提升核心频率实现,还是通过引入bank group实现的? - 知乎