本来快要考试了,这个周安排复习的。谁知数字逻辑老师临时通知我们要做课程设计。。。。。主要是由于我过于自大的原因,没有像同学们那样去网上复制课题,完全自己原创,搞得我焦头烂额,不过结局还好,课题通过了。
本次课程设计题目随便,看到所有人都选的秒表,我就决定做比他们高级的——主支干道红绿灯控制器(包括倒计时的计时器)
用VHDL语言实现的各个模块。
先是控制模块
clk:时钟输入信号
x,y,z:计算器反馈的进位输入端
reset:清零信号低有效
jinji:紧急信号
T1,T2,T3:计数器的始能端
library ieee;
use ieee.std_logic_1164.all;
ENTITY kongzhi IS
PORT(clk,x,y,z: in std_logic;
reset: in std_logic;
A,B,C,D,E,F: out std_logic;
T0,T1,T2: out std_logic;
jinji: in std_logic);
END kongzhi;
ARCHITECTURE beh of kongzhi is
type state is(s0,s1,s2,s3,s4);
signal ns:state;
signal cu:state;
signal t: std_logic_vector(2 downto 0);
signal led: std_logic_vector(5 downto 0);
begin
reg: process(clk,jinji)
begin
if reset='0' then ns<=s0;
elsif clk'event and clk='1' then
if jinji='1'then led<="100100";t<="000";
else
CASE ns is
when s0=>led<="001100"; --绿 红
if x='1' then t<="010";ns<=s1;
else t<="100";ns<=s0;
end if;
when s1=>led<="010100"; --黄 红
if y='1' then t<="001";ns<=s2;
else t<="010";ns<=s1;
end if;
when s2=>led<="100001"; --红 绿
if z='1' then t<="010";ns<=s3;
else t<="001";ns<=s2;
end if;
when s3=>led<="100010"; --红 黄
if y='1' then t<="100";ns<=s0;
else t<="010";ns<=s3;
end if;
when others=>led<="000000";
end CASE;
end if;
A<=led(5);B<=led(4);C<=led(3);D<=led(2);E<=led(1);F<=led(0);
T0<=t(2);T1<=t(1);T2<=t(0);
end if;
end process;
end beh;
然后是三个计数模块
十六进制计数器
Clk为时钟信号输入端,clr为清零端(低有效),en为计数始能端,ql[3..0]为计数输出端,co为进位输出端。
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY s_16 IS
PORT(clk,clr : in std_logic;
en : in std_logic;
ql : out std_logic_vector(3 downto 0);
co : out std_logic);
END s_16;
ARCHITECTURE rtl of s_16 IS
SIGNAL qcl:std_logic_vector(3 downto 0);
BEGIN
PROCESS(clk)
BEGIN
IF(clr='0')THEN
qcl<="1111";
ELSIF(clk'event and clk='1')THEN
IF(en='1')THEN
IF(qcl="0000")THEN
qcl<="1111";
ELSE
qcl<=qcl-'1';
END IF;
END IF;
END IF;
ql<=qcl;
END PROCESS;
co<='1' when qcl="0000" else
'0';
END rtl;
十二进制计数器
Clk为时钟信号输入端,clr为清零端低有效,en为计数使能端,ql[3..0]为计数输出端,co为进位输出端。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity s_12 is
port(clk,clr: in std_logic;
en: in std_logic;
ql: out std_logic_vector(3 downto 0);
co: out std_logic);
end s_12;
ARCHITECTURE rtl of s_12 is
signal qcl:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(clr='0') then
qcl<="1011";
elsif(clk'event and clk='1') then
if(en='1') then
if(qcl="0000") then
qcl<="1011";
else
qcl<=qcl-'1';
end if;
end if;
end if;
ql<=qcl;
end process;
co<='1' when qcl="0000" else
'0';
end rtl;
六进制计数器
Clk为时钟信号输入端clr为清零端低有效,en为计数使能端,ql[3..0]为计数输出端,co为进位输出端。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity s_6 is
port(clk,clr: in std_logic;
en: in std_logic;
ql: out std_logic_vector(3 downto 0);
co: out std_logic);
end s_6;
ARCHITECTURE rtl of s_6 is
signal qcl:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(clr='0') then
qcl<="0101";
elsif(clk'event and clk='1') then
if(en='1') then
if(qcl="0000") then
qcl<="0101";
else
qcl<=qcl-'1';
end if;
end if;
end if;
ql<=qcl;
end process;
co<='1' when qcl="0000" else
'0';
end rtl;
模五计数器
Clk为时钟输入端,clr为清零端,en为计数使能端,QL[2..0]为计数输出端,co为进位输出端。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY mo5 IS
PORT(clk,clr: in std_logic;
en: in std_logic;
ql: out std_logic_vector(2 downto 0);
co: out std_logic);
END mo5;
ARCHITECTURE rtl of mo5 IS
SIGNAL qcl: std_logic_vector(2 downto 0);
BEGIN
PROCESS(clk)
BEGIN
IF(clr='0')THEN
qcl<="000";
ELSIF(clk'event and clk='1')THEN
IF(en='1')THEN
IF(qcl="100")THEN
qcl<="000";co<='1';
ELSE
qcl<=qcl+'1';co<='0';
END IF;
END IF;
END IF;
ql<=qcl;
END PROCESS;
END rtl;
五选一计数器
D0[3..0]到D4[3..0]为输入端,SEL[2..0]为选择的信号
library ieee;
use ieee.std_logic_1164.all;
entity mux5_1 is
port(d0: in std_logic_vector(3 downto 0);
d1: in std_logic_vector(3 downto 0);
d2: in std_logic_vector(3 downto 0);
d3: in std_logic_vector(3 downto 0);
d4: in std_logic_vector(3 downto 0);
sel: in std_logic_vector(2 downto 0);
y: out std_logic_vector(3 downto 0));
end mux5_1;
ARCHITECTURE rtl of mux5_1 is
begin
process(d0,d1,d2,d3,d4,sel)
begin
if(sel="000") then
y<=d0;
elsif(sel="001") then
y<=d1;
elsif(sel="010") then
y<=d2;
elsif(sel="011") then
y<=d3;
else
y<=d4;
end if;
end process;
end rtl;
BCD显示译码器
BCDM[3..0]为BCD码输入端,ABCDEFG为相应的输出端,接在数码管的引脚上
library ieee;
use ieee.std_logic_1164.all;
entity bcd_7dis is
port(bcdm : in std_logic_vector(3 downto 0);
a,b,c,d,e,f,g: out std_logic);
end bcd_7dis;
ARCHITECTURE art of bcd_7dis is
signal w:std_logic_vector(6 downto 0);
begin
process(bcdm)
begin
a<=w(6);b<=w(5);c<=w(4);d<=w(3);e<=w(2);f<=w(1);g<=w(0);
CASE bcdm is
when "0000"=>w<="1111110";
when "0001"=>w<="0110000";
when "0010"=>w<="1101101";
when "0011"=>w<="1111001";
when "0100"=>w<="0110011";
when "0101"=>w<="1011011";
when "0110"=>w<="1011111";
when "0111"=>w<="1110000";
when "1000"=>w<="1111111";
when "1001"=>w<="1111011";
when others=>w<="0000000";
end CASE;
end process;
end art;
之后在锁定引脚,试验箱连线,下载试验箱,如果前面没出问题,应该可以在实验箱上看到红绿灯和倒计时的计时器了
最后程序有个美中不足,那就是三个计时器反馈到控制器的信号最好分频,要加个分频器,不加会出现信号交叉的现象,这里要加个分频器
library ieee;
use ieee.std_logic_1164.all;
entity fenpin is
port(clr,clk: in bit;q: buffer bit);
end fenpin;
architecture a of fenpin is
signal counter:integer range 0 to 49999;
begin
process(clr,clk)
begin
if (clk='1' and clk'event) then
if clr='1' then
counter<=0;
elsif counter=49999 then
counter<=0;
q<= not q;
else
counter<=counter+1;
end if;
end if;
end process;
end a;
最后因为时间问题没把这个模块加上去,不过老师说我能做到这种程度已经很好了。
在这几天为了课题,我一直在实验室里度过的,也没少麻烦老师,说实话,开始不太喜欢这个老师的(总是板着脸,也不笑....)不过这几天出现问题向她询问的时候,她总是很耐心的给我讲解,让我很感动啊。
最后答疑环节,老师让我直接过了,也没问问题,可能是她能问的,我在之前都问过她了........
最后的最后,帮班里的同学看了看他们上网copy的课题及程序,给他们总结了重点,猜测了一下答疑时老师问的问题。结局挺可喜可贺的,全班都通过了。
下个星期一二三四,连续四天考试,感觉没有什么压力,毕竟学霸还是有学霸的好处的(专科老师出题出的尽量简单),要是挂科了我才会惊奇呢·。