IPU相关知识(一)

IPU

参考：http://blog.csdn.net/yanbixing123/article/details/52290933

The i.MX 6DualPlus/6QuadPlus implements a robust muxing logic on the four display 
 ports (2x per IPU), to the external interfaces, either direct, or via bridges (MIPI, LVDS, 
  HDMI), per description below: 


    •  Two parallel - driven directly by each of the IPUs; pixel clock at least up to 200 MHz  两个并口
      (for external load of up to 10 pF). 
         •  Parallel interface works up to 200 MHz 
         •  HDMI interface works up to 240 MHz (IPU) 
    •  Two LVDS channels, driven by the LDB; pixel clock up to 170 MHz. 
    •  One HDMI port (ver. 1.4) - driven by the HDMI transmitter: pixel clock up to 264 
      MHz (gated by the IPU capabilities) 
    •  One MIPI/DSI port - driven by the MIPI/DSI transmitter; 2 data lanes at 1 GHz 
    •  Each IPU display port (DI) can be connected to each of the above ports 

•  Each IPU has 2 display ports, up to four external ports can be active at any given  每个IPU支持2个DSI，扩展为支持4个口
                                    time. (Additional asynchronous data flows can be sent though the parallel ports 
                                    and the MIPI/DSI port.) 
                                 •  Read access is supported as follows 
                                        •  For the Parallel0 port: through DI00 
                                        •  For the Parallel1 port: through DI10 
                                        •  For the MIPI/DSI port: through DI01 or DI11 

Each IPU has two input ports, CSI0 and CSI1, which can receive data concurrently and  每个IPU有2个CSI
independently. At any given time, an IPU input port may receive data either from a 
parallel external port or from the MIPI/CSI-2 receiver. 


The MIPI/CSI-2 port can receive up to 4 concurrent data channels. Each data channel is 
routed to a different CSI input of the IPU (2 IPUs, 2 CSIs on each IPU; a total of 4 CSI 
inputs). Pixel data can be further processed by the IPU. Other data types can be 
transferred through a CSI transparently as generic data to the system memory. 


The IPUs, VPU, VDOA and the GPUs have master AXI ports, providing access to 
system memory.