<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title><![CDATA[aaa23d1的博客]]></title><description><![CDATA[]]></description><link>https://blog.csdn.net/aaa23d1</link><language>zh-cn</language><generator>https://blog.csdn.net/</generator><copyright><![CDATA[Copyright &copy; aaa23d1]]></copyright><item><title><![CDATA[关于低功耗设计]]></title><link>https://blog.csdn.net/aaa23d1/article/details/129784501</link><guid>https://blog.csdn.net/aaa23d1/article/details/129784501</guid><author>aaa23d1</author><pubDate>Tue, 28 Mar 2023 11:02:01 +0800</pubDate><description><![CDATA[本文介绍了功耗类型，IC设计中的低功耗，Xilinx FPGA的低功耗设计。]]></description><category></category></item><item><title><![CDATA[vivado 一文归纳出时序约束]]></title><link>https://blog.csdn.net/aaa23d1/article/details/129770554</link><guid>https://blog.csdn.net/aaa23d1/article/details/129770554</guid><author>aaa23d1</author><pubDate>Sun, 26 Mar 2023 14:14:10 +0800</pubDate><description><![CDATA[vivado 一文归纳出时序约束 包括主时钟以及异步时钟组、多周期约束、伪路径约束等]]></description><category></category></item><item><title><![CDATA[时序违例在FPGA开发流程的分析及解决，结合实际工程]]></title><link>https://blog.csdn.net/aaa23d1/article/details/129721352</link><guid>https://blog.csdn.net/aaa23d1/article/details/129721352</guid><author>aaa23d1</author><pubDate>Sat, 25 Mar 2023 00:08:34 +0800</pubDate><description><![CDATA[本文介绍了VIVADO各个阶段所要注意的影响时序的因素，并根据时序报告的几个重要参数给出相应解决方法。]]></description><category></category></item><item><title><![CDATA[TCL总结(ug835 ug894)]]></title><link>https://blog.csdn.net/aaa23d1/article/details/129712867</link><guid>https://blog.csdn.net/aaa23d1/article/details/129712867</guid><author>aaa23d1</author><pubDate>Thu, 23 Mar 2023 20:02:54 +0800</pubDate><description><![CDATA[TCL总结(ug835 ug894)]]></description><category></category></item><item><title><![CDATA[verilog中的3种for循环的写法]]></title><link>https://blog.csdn.net/aaa23d1/article/details/129290544</link><guid>https://blog.csdn.net/aaa23d1/article/details/129290544</guid><author>aaa23d1</author><pubDate>Wed, 01 Mar 2023 22:06:01 +0800</pubDate><description><![CDATA[verilog中的3种for循环的写法]]></description><category></category></item><item><title><![CDATA[mac/pcs/pma自环的参数配置（1588mac和非1588mac）UG476和PG157]]></title><link>https://blog.csdn.net/aaa23d1/article/details/129085731</link><guid>https://blog.csdn.net/aaa23d1/article/details/129085731</guid><author>aaa23d1</author><pubDate>Fri, 17 Feb 2023 17:45:26 +0800</pubDate><description><![CDATA[mac/pcs/pma自环的参数配置（1588mac和非1588mac）UG476和PG157]]></description><category></category></item><item><title><![CDATA[关于7系列FPGA GT 高速收发器的一些认识（三）]]></title><link>https://blog.csdn.net/aaa23d1/article/details/128290600</link><guid>https://blog.csdn.net/aaa23d1/article/details/128290600</guid><author>aaa23d1</author><pubDate>Fri, 10 Feb 2023 21:23:22 +0800</pubDate><description><![CDATA[关于7系列FPGA GT 高速收发器的一些认识，前面讲了GT的一些基本概念以及复位，这一节介绍GT的时钟，包括时钟间的关系。]]></description><category></category></item><item><title><![CDATA[关于7系列FPGA GT 高速收发器的一些认识（二）]]></title><link>https://blog.csdn.net/aaa23d1/article/details/128223185</link><guid>https://blog.csdn.net/aaa23d1/article/details/128223185</guid><author>aaa23d1</author><pubDate>Mon, 12 Dec 2022 16:53:16 +0800</pubDate><description><![CDATA[这篇先结合工程代码介绍一下GT 高速收发器的复位。大家可以参考UG476，GT的复位有两个模式，下面以常用的Sequential mode为例。]]></description><category></category></item><item><title><![CDATA[关于复位和初始化的总结，贯穿整个项目经历，希望对你有用]]></title><link>https://blog.csdn.net/aaa23d1/article/details/128155016</link><guid>https://blog.csdn.net/aaa23d1/article/details/128155016</guid><author>aaa23d1</author><pubDate>Fri, 02 Dec 2022 22:03:50 +0800</pubDate><description><![CDATA[总结的有关复位的使用建议以及踩的坑和一些比较偏僻的知识点]]></description><category></category></item><item><title><![CDATA[关于keep，dont touch和max_fanout的用法建议]]></title><link>https://blog.csdn.net/aaa23d1/article/details/127982202</link><guid>https://blog.csdn.net/aaa23d1/article/details/127982202</guid><author>aaa23d1</author><pubDate>Tue, 22 Nov 2022 15:53:43 +0800</pubDate><description><![CDATA[关于keep = "true"，don't touch = "true"，max_fanout等命令，项目中只是去用，并没有去了解怎么正确的使用，在翻阅了一些资料以后，针对一些问题做了一些仿真，在这里做一下总结 。]]></description><category></category></item><item><title><![CDATA[调试bug发现关于复位和初始化的一些问题以及建议（important）]]></title><link>https://blog.csdn.net/aaa23d1/article/details/127948046</link><guid>https://blog.csdn.net/aaa23d1/article/details/127948046</guid><author>aaa23d1</author><pubDate>Tue, 22 Nov 2022 11:21:29 +0800</pubDate><description><![CDATA[博主由于做的项目中出现很多关于复位的问题，所以最近看了好多复位的资料，也做了仿真，做了一些总结，网上也很难系统的查到，现在把这些东西分享出来。]]></description><category></category></item><item><title><![CDATA[ram_style的使用]]></title><link>https://blog.csdn.net/aaa23d1/article/details/127862035</link><guid>https://blog.csdn.net/aaa23d1/article/details/127862035</guid><author>aaa23d1</author><pubDate>Tue, 15 Nov 2022 13:54:16 +0800</pubDate><description><![CDATA[ram_style的使用，综合的时候实现该寄存器是用的LUT资源和FF触发器，FF触发器板子资源够用，但是LUT资源不够用，用BRAM实现这个寄存器块]]></description><category></category></item><item><title><![CDATA[VIVADO 综合优化掉模块或者综合太长的原因]]></title><link>https://blog.csdn.net/aaa23d1/article/details/127773045</link><guid>https://blog.csdn.net/aaa23d1/article/details/127773045</guid><author>aaa23d1</author><pubDate>Wed, 09 Nov 2022 16:58:14 +0800</pubDate><description><![CDATA[VIVADO 综合优化掉模块或者综合太长的原因]]></description><category></category></item><item><title><![CDATA[分频时钟、使能时钟、门控时钟的概念和使用]]></title><link>https://blog.csdn.net/aaa23d1/article/details/127753223</link><guid>https://blog.csdn.net/aaa23d1/article/details/127753223</guid><author>aaa23d1</author><pubDate>Tue, 08 Nov 2022 17:47:26 +0800</pubDate><description><![CDATA[FPGA的时钟和时序以及功能息息相关，下面将介绍分频时钟，使能时钟以及门控时钟。]]></description><category></category></item><item><title><![CDATA[亚稳态之跨时钟域处理（二）]]></title><link>https://blog.csdn.net/aaa23d1/article/details/127734513</link><guid>https://blog.csdn.net/aaa23d1/article/details/127734513</guid><author>aaa23d1</author><pubDate>Mon, 07 Nov 2022 17:44:38 +0800</pubDate><description><![CDATA[上一节已经介绍了亚稳态的概念以及跨时钟域单bit信号处理的方式，这一节介绍跨时钟域多bit信号处理的方式。]]></description><category></category></item><item><title><![CDATA[亚稳态之跨时钟域处理（一）]]></title><link>https://blog.csdn.net/aaa23d1/article/details/127654463</link><guid>https://blog.csdn.net/aaa23d1/article/details/127654463</guid><author>aaa23d1</author><pubDate>Thu, 03 Nov 2022 20:53:45 +0800</pubDate><description><![CDATA[为了确保在时钟沿进行可靠稳定的操作，需要数据在时钟沿的前后稳定不变，时钟沿前数据应该保持不变的时间称为建立时间（Tsu），时钟沿后数据应该保持不变的时间称为保持时间（Th）。]]></description><category></category></item><item><title><![CDATA[FIFO的使用及理解]]></title><link>https://blog.csdn.net/aaa23d1/article/details/127632447</link><guid>https://blog.csdn.net/aaa23d1/article/details/127632447</guid><author>aaa23d1</author><pubDate>Tue, 01 Nov 2022 18:55:21 +0800</pubDate><description><![CDATA[先入先出的一个数据存储缓冲器，和RAM不同的是，FIFO的数据被读走了FIFO就空了，而RAM的数据可以反复读。本次内容是基于Xilinx的官方IP-FIFO Generator。]]></description><category></category></item><item><title><![CDATA[接上篇 SSI技术及调试中的BUFMR和BUFR布局布线问题]]></title><link>https://blog.csdn.net/aaa23d1/article/details/127511779</link><guid>https://blog.csdn.net/aaa23d1/article/details/127511779</guid><author>aaa23d1</author><pubDate>Tue, 25 Oct 2022 18:36:47 +0800</pubDate><description><![CDATA[SSI技术及调试中的BUFMR和BUFR布局布线问题]]></description><category></category></item><item><title><![CDATA[终于理清 异步复位，同步释放]]></title><link>https://blog.csdn.net/aaa23d1/article/details/127449856</link><guid>https://blog.csdn.net/aaa23d1/article/details/127449856</guid><author>aaa23d1</author><pubDate>Fri, 21 Oct 2022 19:03:43 +0800</pubDate><description><![CDATA[终于理清 异步复位，同步释放]]></description><category></category></item><item><title><![CDATA[7系列FPGA时钟资源新手入坑版 UG472]]></title><link>https://blog.csdn.net/aaa23d1/article/details/127397829</link><guid>https://blog.csdn.net/aaa23d1/article/details/127397829</guid><author>aaa23d1</author><pubDate>Wed, 19 Oct 2022 13:33:24 +0800</pubDate><description><![CDATA[7系列FPGA时钟资源新手入坑版 UG472]]></description><category></category></item></channel></rss>