嵌入式系统设计的阅读资料（to be done）

Embedded System Design Methodology

 

1. Introduction   

[1] Kurt Keutzer, et. al. "System-Level Design: Orthogonalization of Concerns and Platform-Based Design," IEEE TCAD, 19   (12), December 2000. 
[2] Stephen Edwards, et. al. "Design of Embedded Systems: Formal Models, Validation, and Synthesis," Proceedings of the IEEE, 85(3), March 1997. 
[3] W. Wolf, "Modern VLSI Design: System-on-Chip Design", Prentice Hall, 2002. 
[4] D. Densmore, A. Sangiovanni-Vincentelli, and R. Passerone, "A Platform-Based Taxonomy for ESL Design," IEEE Design&Test, (23)5, pp. 359-374, September, 2006. 
[5] B. Bailey, G. Martin, and T. Anderson, "Taxonomies for the Development and Verification of Digital Systems," Springer, 2005. 
[6] M. Burton and A. Morawiec, "Platform Based Design at the Electronic System Level," Springer, 2006. 
[7] J. Rowson and A. Sangiovanni-Vincentelli, "Interface-based design," 34th DAC 1997 


  2. System Modeling Language: SystemC 

[8] L. Cai and D. Gajski, "Transaction Level Modeling: An Overview," CODES+ISSS 2003, pp.19-24, October, 2003 
[9] F. Ghenassia, "Transaction-Level Modeling with SystemC," Springer, 2005. 
[10] 기안도, "SystemC 시스템 모델링 언어," 대영사 2004. 


  3. HW/SW Cosimulation   
     
[11] Dohyung Kim, Chae-Eun Rhee, and Soonhoi Ha, "Combined Data-driven and Event-driven Scheduling Technique for Fast Distributed Cosimulation,"  IEEE Transactions on Very large Scale Integration(VLSI) Systems Vol. 10 pp 672-679 October 2002.   
[12] Youngmin Yi, Dohyung Kim, and Soonhoi Ha, "Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual Synchronization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Accepted in 2007 .   


  4. C-based Design (lecture_note 4) 


  5. Dataflow Model and Software Synthesis 

[13] E.A.Lee and D.G.Messerschmitt, "Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing," IEEE Computer, January 1987. 
     E.A.Lee and D.G.Messerschmitt, "Synchronous Data Flow", IEEE Proceedings, September, 1987 
[14] Jose Luis Pino, Soonhoi Ha, Edward A. Lee, and Joseph T. Buck, "Software Synthesis for DSP Using Ptolemy,"Journal on VLSI Signal Processing, vol. 9, no. 1, pp. 7-21, January, 1995. . 
[15] Chanik Park, et. al., "Extended Synchronous Dataflow for Efficient DSP System Prototyping," Design Automation for Embedded Systems, Kluwer Academic Publishers, pp.295-322,March 2002. 
[16] Hyunok Oh and Soonhoi Ha, "Fractional rate dataflow model for efficient code synthesis", Journal of Vlsi Signal Processing Systems for Signal Image and Video Techno Vol. 37 pp 41-51 May. 2004 
[17] Hyunok Oh and Soonhoi Ha, "Memory-optimized Software Synthesis from Dataflow Program Graphs with Large Size Data Samples", EURASIP Journal on Applied Signal Processing Vol. 2003 pp 514-529 May 2003 
[18] G. Bilsen, et. al., "Cyclo-Static Dataflow," IEEE TSP, 44(2), February 1996. 
[19] PeaCE overview, http://peace.snu.ac.kr/research/peace/data/summary/peace.pdf 


  6. HW and Interface Synthesis   

[19] Hyunuk Jung and Soonhoi Ha, "Hardware Synthesis From Coarse-Grained Dataflow Specification For Fast HW/SW Cosynthesis", CODES+ISSS'04 pp 24-29 September 2004   
[20] Hyunuk Jung, Hoeseok Yang, and Soonhoi Ha, "Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis", Journal of VLSI Signal Processing (online published) 10, June. 2007 


  7. Models of Computation and Design Environments 

[21] E. A. Lee and A. Sangiovanni-Vincentelli, "A Framework for Comparing Models of Computation," IEEE TCAD, 17(12), December, 1998. 
[22] D.Harel, "Statecharts: A visual formalism for complex systems", Science of Computer Programming, Vol. 8, pp. 231-274, 1987 
[23] STATEMATE: David Harel, et. al., "STATEMATE: A Working Environment for the Development of Complex Reactive Systems," IEEE TSE, 16(4), April 1990. 
[24] POLIS & ACFSM: Marco Sgroi, Luciano Lavagno, A. Sangiovanni-Vincentelli, "Formal Models for Embedded System Design," IEEE Design & Test of Computers, 17(2), 14-27, June 2000. 
[25] COSY: H.J.H.N.Kenter et. al, "Designing Digital Video Systems: Modeling and Scheduling," CODES Workshop, May 1999. 
[26] Simulink: Paul Caspi, et. al, "Translating Discrete-Time Simulink to Lustre," LNCS, Vol. 2855/2003, pp. 84-99, 2003. 
[27] W.Chang, S.Ha, and E.A.Lee, "Heterogeneous Simulation - Mixing Discrete-Event Models with Dataflow", RASSP Special Issue of VLSI Signal Processing, January, 1997. 
[28] Ptolemy *chart: A. Girault, B. Lee, and E. A. Lee, ``Hierarchical Finite State Machines with Multiple Concurrency Models,'' IEEE Transactions On Computer-aided Design Of Integrated Circuits And Systems, Vol. 18, No. 6, June 1999. 
[29] E. A. Lee and T. M. Parks, "Dataflow Process Networks," Proceedings of the IEEE, vol. 83, no. 5, pp. 773-801, May, 1995. 

   
  8. Model based Design of Embedded SW 

[30] Dohyung Kim, Minyoung Kim and Soonhoi Ha, "A Case Study of System Level Specification and Software Synthesis of Multi-mode Multimedia Terminal", Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), Newport Beach, CA, USA Oct 2003 
[31] Jie Liu and Edward A. Lee, "Timed Multitasking for Real-Time Embedded Software," IEEE Control Systems Magazine, pp. 65-75, February 2003. 
[32] T.A.Henzinger, B.Horowitz, and C.M.Kirsch, "Embedded Control Systems Development with Giotto," LCTES (Languages, Compilers, and Tools for Embedded Systems) Proceedings, pp. 64-72, June, 2001. 


  9. Design Space Exploration   

[33] Hyunok Oh and Soonhoi Ha, "A Hardware-Software Cosynthesis Technique Based on Heterogeneous Multiprocessor Scheduling," CODES Workshop, May 1999. 
[34] Hyunok Oh and Soonhoi Ha, "Hardware-Software Cosynthesis of Multi-Mode Multi-Task Embedded Systems with Real-Time Constraints", CODES, 2002   
[35] Sungchan Kim, Chaeseok Im, and Soonhoi Ha, "Schedule-Aware Performance Estimation of Communication Architecture for Efficient Design Space Exploration", IEEE Transactions on Very Large Scale Integration systems, Vol. 13 pp 539-552 May 2005 
[36] SungChan Kim and Soonhoi Ha, "Efficient Exploration of Bus-Based System-on-Chip Architectures", IEEE Transactions on Very Large Scale Integration systems, Vol. 14 pp 681-692 July 2006 

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