anqi8955的专栏

This document describes the Host Processor Interface (HPI) implemented by Cypress’ CCG USB Type-C and USB Power Delivery (PD) controllers. This includes description of HPI Transport, Protocol, Registers and PD Message Handling. CCG devices are commonly used in PD port controller applications in systems like Notebook and Desktop computers, tablets, mobiles etc. In such cases, the system design typically includes a Host Processor or Embedded Controller (EC) that is responsible for the system polic

The Unicode Standard, Version 15.0

acpi最新规范(2022.8.29),已解锁

uefi最新规范(2022.8.29)，已解锁

RK3588全套硬件设计资料

This Design Guide provides motherboard implementation recommendations for the Kaby Lake platform, based on the Kaby Lake processor. This document includes design guides for Kaby Lake (KBL) U and Kaby Lake Y platforms.The Kaby Lake processors will enable the next generation of 2-in-1s and Ultrabook.

Windows Internals, Seventh Edition is intended for advanced computer professionals (developers,security researchers, and system administrators) who want to understand how the core components of theMicrosoft Windows 10 and Windows Server 2016 operating systems work internally. With thisknowledge, developers can better comprehend the rationale behind design choices when buildingapplications specific to the Windows platform. Such knowledge can also help developers debug complexproblems.

ASR1601是一款高性价比的片上系统（SOC）设备，集成了应用程序处理子系统，通信子系统，音频编解码器和嵌入式pSRAM，以支持单芯片4G LTE功能电话解决方案以及GSM解决方案。 该通信子系统集成了LTE CAT1，GSM调制解调器基带和RF收发器，覆盖450MHz〜2.7GHz频段，可在全球范围内漫游。 该应用子系统运行在Cortex-R5处理器上，该处理器具有集成的多媒体组件，包括摄像头系统，ISP，视频播放/编码，显示控制器和音频编解码器。此外，还提供了广泛的接口和连接外围设备集，可与摄像头，显示器， MMC / sd卡，传感器，wifi，FM收音机，蓝牙等。

统一可扩展固件接口(UEFI)规范描述了操作系统和平台固件之间的接口。UEFI之前是可扩展固件接口规范1.10 (EFI)。因此，一些代码和某些协议名称保留了EFI名称。除非另有说明，本规范中的EFI名称可能被认为是UEFI的一部分。 接口采用数据表的形式，其中包含与平台相关的信息，以及OS加载器和OS可用的引导和运行时服务调用。它们共同提供了一个引导操作系统的标准环境。本规范是作为一个纯粹的接口规范设计的。因此，该规范定义了平台固件必须实现的接口和结构集。类似地，该规范定义了操作系统在引导时可能使用的一组接口和结构。固件开发人员如何选择实现所需的元素，或者操作系统开发人员如何选择利用这些接口和结构，这是留给开发人员的实现决策。 该规范的目的是定义一种方法，使操作系统和平台固件仅通信支持操作系统引导过程所必需的信息。这是通过平台和固件提供给操作系统的软件可见接口的正式和完整的抽象规范来实现的。 使用这一正式定义，旨在运行在与受支持的处理器规范兼容的平台上的收缩包装操作系统将能够在各种系统设计上启动，而无需进一步的平台或操作系统定制。该定义还允许平台创新引入新特性和功能，以增强平台的能力，而不需要按照操作系统的引导顺序编写新代码。 此外，抽象规范开辟了一条替代遗留设备和固件代码的路径。新的设备类型和相关代码可以通过相同定义的抽象接口提供同等的功能，同样不会影响OS引导支持代码。 该规范适用于从移动系统到服务器的所有硬件平台。该规范提供了一组核心服务以及一组协议接口。协议接口的选择可以随着时间的推移而发展，并针对不同的平台市场细分进行优化。与此同时，该规范允许oem提供最大限度的可扩展性和定制能力，以实现差异化。在这方面，UEFI的目的是定义一个从传统的“PC-AT”风格的引导世界到一个没有遗留api的环境的进化路径。

此文章由丹心静居下载整理，虽然是 16.2 版本的，只要你掌握了设计流程和方法，学 会 16.3 到 16.6 版本的不再是难事（想学精通，需要自己加倍努力），只是个别界面有些区别 而已，所以很值得推荐给大家学习一下，文内有实例操作，操作截图，截图清晰，容易理解， 让你不再为学习 Cadence 软件发愁。

IT8768_datasheet.pdf

ACPI的历史ACPI是在20世纪90年代中期由Intel, Microsoft*， Toshiba*， HP*和Phoenix*合作开发的。在开发ACPI之前，操作系统主要使用BIOS (Basic Input/Output System)接口进行电源管理、设备发现和配置。电源管理的方法是利用操作系统调用系统BIOS的能力来进行电源管理。BIOS还用于根据探测输入/输出(I/O)来发现系统设备和加载驱动程序，并尝试将正确的驱动程序匹配到正确的设备(即插即用)。设备的位置也可以在BIOS中硬编码，因为平台本身是不可枚举的。这些解决方案在三个关键方面存在问题。首先，操作系统应用程序的行为可能会受到bios配置的电源管理设置的负面影响，导致系统在演示期间或其他不方便的时间进入睡眠状态。第二，电源管理接口是每个系统的专有接口。这要求开发人员了解如何为每个单独的系统配置电源管理。最后，各种设备的默认设置也可能相互冲突，导致设备崩溃、行为不稳定或变得无法发现。

This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 4 Gb through 32 Gb and single channel density ranges from 2 Gb through 16 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2) and LPDDR3 (JESD209-3).

Hi3516EV300 作为新一代行业专用 HD IP 摄像机 SOC，集成新一代 ISP 以及业界最新 的 H.265 视频压缩编码器，同时采用先进低功耗工艺和低功耗架构设计，使得 Hi3516EV300 在低码率、高画质、低功耗等方面引领行业水平。集成 POR、RTC、 Audio Codec，为客户极大的降低了 ebom 成本。且与海思 DVR/NVR 芯片相似的接口 设计，能方便支撑客户产品开发和量产。

Hi3518EV300 作为新一代消费类 Camera SOC，集成新一代 ISP 以及业界最新的 H265 视频压缩编码器，在低码率、高画质等方面领先业界，同时人形检测，支持人脸和异 常声音检测等智能应用；采用先进低功耗工艺和低功耗架构设计，使得 Hi3518EV300 在低功耗上引领行业水平。集成 POR、RTC、Audio Codec，为客户极大的降低了 ebom 成本。

This Design Guide provides motherboard implementation recommendations for the Kaby Lake platform, based on the Kaby Lake processor. This document includes design guides for Kaby Lake (KBL) U and Kaby Lake Y platforms. The Kaby Lake processors will enable the next generation of 2-in-1s and Ultrabook. The Kaby Lake platform consists of KBL U and KBL Y 1-Chip Platform Series, KBL H 2- Chip Platform Series and KBL S 2-Chip Platform Series. The Kaby Lake U platform consists of a Kaby Lake U processor plus a Kaby Lake Platform Controller Hub (PCH) in the same Multi Chip Package (MCP). Kaby Lake PCH, also known as KBL PCH, refers to the PCH portion of the Kaby Lake processor. Similarly the Kaby Lake Y platform consists of a Kaby Lake Y processor plus a Kaby Lake PCH in the same Multi Chip Package (MCP). The Kaby Lake H and S 2-Chip platform consists of KBL processor package with Kaby Lake PCH package.

The BD99950MUV is a high-efficiency, synchronous Narrow VDC system voltage regulator and battery charger controller. It has two charge pumps which separately drive N-channel MOSFETs for automatic system power source selection. Charge voltage, charge current, AC adapter current and minimum system voltage can be programmed through SMBus. With a small inductor, PWM switching frequency can also be programmed by SMBus up to 1.2MHz

The RT5077A is a highly-Integrated multi-channel power management solutions to meet the performance, efficiency and feature requirements for INTEL GLK platform. This device provides 2 step-down controllers, 4 step-down converters, 1 LDO and 1 load switch in one package.

The RT5077A is a highly-Integrated multi-channel power management solutions to meet the performance, efficiency and feature requirements for INTEL GLK platform. This device provides 2 step-down controllers, 4 step-down converters, 1 LDO and 1 load switch in one package.

对 DDR2 SDRAM的访问是基于突发模式的; 读写时，选定一个起始地址，并按照事先编程设定的突发长度（4或8）和突发顺序来依次读写.访问操作开始 一个激活命令, 后面紧跟的就是读或者写命令。和激活命令同步送达的地址位包含了所要存取的簇和行 (BA0, BA1 选定簇; A0-A13 选定行). 和读或写命令 同步送达的地址位包含了突发存取的起始列地址 ，并决定是否发布自动预充电命令。 在进行常用的操作之前, 要先对 DDR2 SDRAM 进行初始化. 下面的几小节介绍初始化的详细信息，寄存器的定义，命令的描述和芯片的操作。

UEFI_Spec_2_8_final.pdf

在本规范中，假设视听内容是通过基于 HDMI 的有线显示链路传输的。在 HDCP 系统中，两 个或多个 HDCP 设备通过 HDCP 保护接口相互连接。视听内容从上游内容控制功能流向最上 游 HDCP 发射机的 HDCP 系统。从那里，由 HDCP 系统加密的视听内容(称为 HDCP 内容)在 HDCP 保护的接口上流经一个树形的 HDCP 接收器拓扑。本规范描述了一种内容保护机 制:(1)HDCP 接收器的身份验证到其直接的上游连接(即:(2)由数字内容保护有限责任公司(LLC) 决定的 HDCP 接收器的撤销无效，和(3)HDCP 加密视听内容在 HDCP 保护接口之间的 HDCP 发射器

w25q64fw_revk 07012016 sfdp.pdf

You may freely use these code charts for personal or internal business uses only. You may not incorporate them either wholly or in part into any product or publication, or otherwise distribute them without express written permission from the Unicode Consortium. However, you may provide links to thes

Hi3519AV100 是一颗面向监控 IP 摄像机、运动相机、全景相机、后视镜等多个产品领域推出的高性能、低功耗的 4K Smart Camera SoC。该芯片支持H.265/H.264 编解码，编码/解码性能高达 4K*2K@60fps/1080p@240fps；该芯片集成了海思第四代 ISP，支持 WDR、多级降噪、六轴防抖及多种图像增强和矫正算法，为客户提供专业级的图像质量。同时，该芯片还支持 4K RAW 数据输出，可用于影片后期编辑。该芯片采用先进的 12nm 低功耗工艺和低功耗架构设计，简化客户产品的散热设计，有利于客户打造节能环保的智能摄像机产品。

MotionInterface™ is becoming a “must-have” function being adopted by smartphone and tablet manufacturers due to the enormous value it adds to the end user experience. In smartphones, it finds use in applications such as gesture commands for applications and phone control, enhanced gaming, augmented

Hi3516DV300 作为新一代行业专用 Smart HD IP 摄像机 SOC，集成新一代 ISP、业界 最新的 H.265 视频压缩编码器，同时集成高性能 NNIE 引擎，使得 Hi3516DV300 在低 码率、高画质、智能处理和分析、低功耗等方面引领行业水平。集成 POR、RTC、 Audio Codec 以及待机唤醒电路，为客户极大的降低了 ebom 成本。且与海思 DVR/NVR 芯片相似的接口设计，能方便支撑客户产品开发和量产。

3516C v300的SDK，大小2个多G，网盘链接， 大家需要可以下载，欢迎大家进行交流。。。。。

This chapter presents an overview of Universal Serial Bus 4 (USB4™) architecture and key concepts. USB4 is similar to earlier versions of USB in that it is a cable bus supporting data exchange between a host computer and a wide range of simultaneously accessible peripherals. However, USB4 also allows a host computer to setup data exchange between compatible peripherals. The attached peripherals share bandwidth as configured by the host computer. The bus allows peripherals to be attached, configured, used, and detached while the host and other peripherals are in operation. When configured over a USB Type-C® connector interface, USB4 functionally replaces USB 3.2 while retaining USB 2.0 bus operating in parallel. Enhanced SuperSpeed USB, as defined in USB 3.2, remains the fundamental architecture for USB data transfer on a USB4 Fabric. The difference with USB4 versus USB 3.2 is that USB4 is a connection -oriented, tunneling architecture designed to combine multiple protocols onto a single physical interface, so that the total speed and performance of the USB4 Fabric can be dynamically shared. USB4 allows for USB data transfers to operate in parallel with other independent protocols specific to display, load/store and host-to-host interfaces. Additionally, USB4 extends performance beyond the 20 Gbps (Gen 2 x 2) of USB 3.2 to 40 Gbps (Gen 3 x 2) over the same dual-lane, dual-simplex architecture. This specification introduces the concept of protocol tunneling to USB bus architecture. Besides tunneling Enhanced SuperSpeed USB (USB3), display tunneling based on DisplayPort (DP) protocol and load/store tunneling based on PCI Express (PCIe) are defined. These protocol tunnels operate independently over the USB4 transport and physical layers. Additionally, USB4 allocates packets for bus configuration and management, and packe ts can be allocated specifically for host-to-host data connections.

Adopters of the USB4™ specification have signed the USB4 Adopters Agreement, which provides them access to a royalty-free reasonable and nondiscriminatory (RAND) license from the Promoters and other Adopters to certain intellectual property contained in products that are compliant with the USB4 specification. Adopters can demonstrate compliance with the specification through the testing program as defined by the USB Implementers Forum (USB -IF). Products that demonstrate compliance with the specification will be granted certain rights to use the USB-IF logos as defined in the logo license.

The RT3602AC is an IMVP8 compliant CPU power controller which includes three voltage rails : a 2/1 phase synchronous Buck controller, the MAIN VR, a single phase synchronous Buck controller, the auxiliary VR, and a single phase synchronous Buck controller, the VCCSA VR. The RT3602AC adopts G-NAVPTM(Green Native AVP) which is Richtek's proprietary topology derived from finite DC gain of EA amplifier with current mode control, making it easy to set the droop to meet all Intel CPU requirements of AVP (Adaptive Voltage Positioning). Based on the GNAVPTM topology, the RT3602AC also features a quick response mechanism for optimized AVP performance during load transient. The RT3602AC supports mode transition function with various operating states. A serial VID (SVID) interface is built in the RT3602AC to communicate with Intel IMVP8 compliant CPU. The RT3602AC supports VID on-the-fly function with three different slew rates : Fast, Slow and Decay. By utilizing the G-NAVPTM topology, the operating frequency of the RT3602AC varies with VID, load and input voltage to further enhance the efficiency even in CCM. Moreover, the GNAVPTM with CCRCOT (Constant Current Ripple COT) technology provides superior output voltage ripple over the entire input/output range. The built-in high accuracy DAC converts the SVID code ranging from 0.25V to 1.52V with 5mV per step. The RT3602AC integrates a high accuracy ADC for platform setting functions, such as quick response trigger level. Besides, the setting function also supposes this two rails address exchange. The RT3602AC provides VR ready output signals. It also features complete fault protection functions including over-voltage (OV), negative voltage (NV), over-current (OC) and under-voltage lockout (UVLO). The RT3602AC is available in the WQFN- 52L 6x6 small foot print package.

LVDS用户手册第四版 National Semiconductor’s LVDS Owner’s Manual, frst published in spring 1997, has been the industry’s “go-to design guide” over the last decade. Te owner’s manual helped LVDS grow from the original IEEE 1596.3-1996 Standard for Low-Voltage Differential Signaling (LVDS) for Scalable Coherent Interface (SCI) into the workhorse technology it is today. LVDS is now pervasive in communications networks and used extensively in applications such as laptop computers, ofce imaging, industrial vision, test and measurement, medical, and automotive. It provides an attractive solution - a small-swing differential signal for fast data transfers at signifcantly reduced power and with excellent noise immunity. Along with the applications, LVDS continued to evolve over the last decade to meet specifc requirements such as Bus LVDS and Multipoint LVDS. For example, the latest LVDS products are capable of data rates in excess of 3 Gbps while still maintaining the low power and noise immunity characteristics. Today, many applications require even faster data rates and longer transmission paths. Terefore, designers should consider technologies such as Current-Mode Logic (CML) and signal conditioning for both LVDS and CML. Tat is why this new Fourth Edition includes practical design techniques for these technologies as well as LVPECL and LVCMOS. Tis owner’s manual provides useful and current information. It begins with a brief overview of the three most common high-speed interface technologies (LVDS (with variants B-LVDS and M-LVDS), CML, and LVPECL) a review of their respective characteristics, and a section on selecting the optimal technology for an application. Te manual then covers relevant topics such as level translation, jitter, signal conditioning, and suggested design approaches. Tis practical information will help you select the right solution for today’s interface design issues.

This standard defines requirements and options of a standardized display panel interface for embedded display applications. It is based on the VESA DisplayPort Standard Version 1.3 and includes implementation options recommended for consideration by the system integrator.

The Keysight Technologies, Inc. eDP 1.4 electrical performance and characterization (EP&C) software for Infniium Series oscilloscopes (see Table 2) provides you with a fast and easy way to verify and debug your eDP interface designs for embedded systems. The eDP 1.4 electrical test software is designed to be uniquely flexible to handle the wide variety of confgurations that are possible in embedded systems and pose characterization challenges. It offers the standard tests that are recommended as well as other informative tests, so it functions equally well as a validation tool. It displays the measurement data results in a flexible report format, and the report also provides a margin analysis that shows how closely your device passed or failed each test.

The IT66351 is a HDMI2.0 3 IN to 1 OUT re-timer switch which supports maximum signaling rate up to 6Gbps/channel. It is compliant to the latest HDMI2.0b specification and backward compatible to the HDMI1.4 and DVI specifications. With 6Gbps/channel capability, the IT66351 can support ultra-high resolution content streams, such as 4Kx2K@50/60Hz video formats. With the re-timer structure, the IT66351 can support superior performance for long cable application. All 3 input ports and 1 output port support HDMI2.0 data rate up to 18Gb/s.

This Unified Extensible Firmware Interface (UEFI) Specification describes an interface between the operating system (OS) and the platform firmware. UEFI was preceded by the Extensible Firmware Interface Specification 1.10 (EFI). As a result, some code and certain protocol names retain the EFI designation. Unless otherwise noted, EFI designations in this specification may be assumed to be part of UEFI. The interface is in the form of data tables that contain platform-related information, and boot and runtime service calls that are available to the OS loader and the OS. Together, these provide a standard environment for booting an OS. This specification is designed as a pure interface specification. As such, the specification defines the set of interfaces and structures that platform firmware must implement. Similarly, the specification defines the set of interfaces and structures that the OS may use in booting. How either the firmware developer chooses to implement the required elements or the OS developer chooses to make use of those interfaces and structures is an implementation decision left for the developer. The intent of this specification is to define a way for the OS and platform firmware to communicate only information necessary to support the OS boot process. This is accomplished through a formal and complete abstract specification of the software-visible interface presented to the OS by the platform and firmware. Using this formal definition, a shrink-wrap OS intended to run on platforms compatible with supported processor specifications will be able to boot on a variety of system designs without further platform or OS customization. The definition will also allow for platform innovation to introduce new features and functionality that enhance platform capability without requiring new code to be written in the OS boot sequence. Furthermore, an abstract specification opens a route to replace legacy devices and firmware code over time. New device types and associated code can provide equivalent functionality through the same defined abstract interface, again without impact on the OS boot support code. The specification is applicable to a full range of hardware platforms from mobile systems to servers. The specification provides a core set of services along with a selection of protocol interfaces. The selection of protocol interfaces can evolve over time to be optimized for various platform market segments. At the same time, the specification allows maximum extensibility and customization abilities for OEMs to allow differentiation. In this, the purpose of UEFI is to define an evolutionary path from the traditional “PC-AT”- style boot world into a legacy-API free environment.

本参考手册面向应用开发人员，提供有关使用 STM32F405xx/07xx、 STM32F415xx/17xx、 STM32F42xxx 和 STM32F43xxx 微控制器存储器与外设的完整信息。 STM32F405xx/07xx、 STM32F415xx/17xx、 STM32F42xxx 和 STM32F43xxx 构成一个微 控制器系列，各产品具有不同的存储器大小、封装和外设。 有关订购信息以及器件的机械与电气特性，请参见数据手册。 有关 ARM Cortex™-M4F 内核的信息，请参见《Cortex™-M4F 技术参考手册》

The Advanced Configuration and Power Interface (ACPI) specification was developed to establish industry common interfaces enabling robust operating system (OS)-directed motherboard device configuration and power management of both devices and entire systems. ACPI is the key element in Operating System-directed configuration and Power Management (OSPM). ACPI evolved the existing pre-ACPI collection of power management BIOS code, Advanced Power Management (APM) application programming interfaces (APIs, PNPBIOS APIs, Multiprocessor Specification (MPS) tables and so on into a well-defined power management and configuration interface specification. ACPI provides the means for an orderly transition from existing (legacy) hardware to ACPI hardware, and it allows for both ACPI and legacy mechanisms to exist in a single machine and to be used as needed. Further, system architectures being built at the time of the original ACPI specification’s inception, stretched the limits of historical “Plug and Play” interfaces. ACPI evolved existing motherboard configuration interfaces to support advanced architectures in a more robust, and potentially more efficient manner. The interfaces and OSPM concepts defined within this specification are suitable to all classes of computers including (but not limited to) desktop, mobile, workstation, and server machines. From a power management perspective, OSPM/ACPI promotes the concept that systems should conserve energy by transitioning unused devices into lower power states including placing the entire system in a low-power state (sleeping state) when possible. This document describes ACPI hardware interfaces, ACPI software interfaces and ACPI data structures that, when implemented, enable support for robust OS-directed configuration and power management (OSPM)

This Unified Extensible Firmware Interface (hereafter known as UEFI) Specification describes an interface between the operating system (OS) and the platform firmware. UEFI was preceded by the Extensible Firmware Interface Specification 1.10 (EFI). As a result, some code and certain protocol names retain the EFI designation. Unless otherwise noted, EFI designations in this specification may be assumed to be part of UEFI. The interface is in the form of data tables that contain platform-related information, and boot and runtime service calls that are available to the OS loader and the OS. Together, these provide a standard environment for booting an OS. This specification is designed as a pure interface specification. As such, the specification defines the set of interfaces and structures that platform firmware must implement. Similarly, the specification defines the set of interfaces and structures that the OS may use in booting. How either the firmware developer chooses to implement the required elements or the OS developer chooses to make use of those interfaces and structures is an implementation decision left for the developer. The intent of this specification is to define a way for the OS and platform firmware to communicate only information necessary to support the OS boot process. This is accomplished through a formal and complete abstract specification of the software-visible interface presented to the OS by the platform and firmware. Using this formal definition, a shrink-wrap OS intended to run on platforms compatible with supported processor specifications will be able to boot on a variety of system designs without further platform or OS customization. The definition will also allow for platform innovation to introduce new features and functionality that enhance platform capability without requiring new code to be written in the OS boot sequence. Furthermore, an abstract specification opens a route to replace legacy devices and firmware code over time. New device types and associated code can provide equivalent functionality through the same defined abstract interface, again without impact on the OS boot support code. The specification is applicable to a full range of hardware platforms from mobile systems to servers. The specification provides a core set of services along with a selection of protocol interfaces. The selection of protocol interfaces can evolve over time to be optimized for various platform market segments. At the same time, the specification allows maximum extensibility and customization abilities for OEMs to allow differentiation. In this, the purpose of UEFI is to define an evolutionary path from the traditional “PC-AT”- style boot world into a legacy-API free environment.

USB内核与PHY之间的接口规范，用于对USB PHY的操作接口，USB技术规发可供参考！USB技术规发可供参考！