Verilog
carldada
这个作者很懒,什么都没留下…
展开
-
Verilog 算数移位运算
参考文件1:Verilog HDL A Guide to Digital Design and Synthesis, Second Edition 第103页原创 2020-11-10 21:26:33 · 710 阅读 · 0 评论 -
惯性延时和传输延时
固有延时也是惯性延时,是任何电子器件都存在的一种延时特性,主要物理机制是分布电容效应。 传输延时:与固有延时相比,其不同之处在于传输延时时表达的是输入与输出之间的一种绝对延时关系。传输延时并不考虑信号持续的时间,它仅表示信号传输推迟或延迟了一个时间段,这个时间段即为传输延时。...原创 2020-11-10 21:16:22 · 3522 阅读 · 0 评论 -
verilog中参数传递与参数定义中#的作用
一、module内部有效的定义用parameter来定义一个标志符代表一个常量,称作符号常量,他可以提高程序的可读性和可维护性。parameter是参数型数据的关键字,在每一个赋值语句的右边都必须是一个常数表达式。即该表达式只能包含数字或先前已经定义的参数。parameter msb=7; //定义参数msb=7parameter r=5.7; //定义r为一个实型参数5.7parameter byte_s...转载 2020-11-10 20:48:58 · 3674 阅读 · 0 评论 -
Verilog 模块的组成
参考文件1:Verilog HDL A Guide to Digital Design and Synthesis, Second Edition 第62页原创 2020-11-10 16:53:48 · 631 阅读 · 0 评论 -
Verilog 数组的访问
reg [4:0] port_id[0:7]; // Array of 8 port_ids; each port_id is 5 bits wide 一维数组,数据长度数5bitport_id[3] = 0; // Reset 3rd element (a 5-bit value) of port_id arrayreg [63:0] array_4d [15:0][7:0][7:0][255:0]; //Four dimensional arrayarray_4d[0][0][0][0][..原创 2020-11-09 22:09:51 · 1241 阅读 · 0 评论 -
Verilog 变量作为数据的下标
Variable Vector Part SelectAnother ability provided in Verilog HDl is to have variable part selects of a vector. Thisallows part selects to be put in for loops to select various parts of the vector. There aretwo special part-select operators:[<start原创 2020-11-09 21:55:00 · 3055 阅读 · 0 评论 -
Verilog $stop $finish
Stopping and finishing in a simulationThe task $stop is provided to stop during a simulation.Usage: $stop;The $stop task puts the simulation in an interactive mode. The designer can then debugthe design from the interactive mode. The $stop task is us原创 2020-11-09 21:42:54 · 954 阅读 · 0 评论 -
Verilog 监控 Monitor
Monitoring informationVerilog provides a mechanism to monitor a signal when its value changes. This facility isprovided by the $monitor task.Usage: $monitor(p1,p2,p3,....,pn);The parameters p1, p2, ... , pn can be variables, signal names, or quoted str原创 2020-11-09 21:39:25 · 1673 阅读 · 0 评论 -
Verilog中的X和Z值
X or Z valuesVerilog has two symbols for unknown and high impedance values. These values are veryimportant for modeling real circuits. An unknown value is denoted by an x. A highimpedance value is denoted by z.12'h13x // This is a 12-bit hex number; 4原创 2020-11-09 21:02:56 · 5568 阅读 · 0 评论 -
Verilog中未指明长度数据的长度
Unsized numbersNumbers that are specified without a <base format> specification are decimal numbersby default. Numbers that are written without a <size> specification have a default numberof bits that is simulator- and machine-specific (must原创 2020-11-09 20:54:08 · 847 阅读 · 0 评论 -
Verilog 带符号的数值运算 乘法器
//1:乘法符号的乘法,根据数据类型来选择乘法器类型,如果A和B都是符号数,则乘法器为带符号乘法器assign r01 = dataA * dataA; //8'b1110 0001assign r02 = dataA * dataB; //8'b1110 0001assign r03 = dataB * dataB; //8'b1 //2:无符号乘法器,将数据转化为无符号数,然后相乘Mult_unsigned Mult_unsigned_inst1 ( .dataa ( da..原创 2020-11-06 19:45:10 · 4766 阅读 · 0 评论 -
Verilog 带符号的数值运算 加法
module TestBench( output signed [9:0] result1, output signed [9:0] result2, output signed [9:0] result3, output [9:0] result4, output [9:0] result5, output [9:0] result6, output [5:0] result7, output [5:0] result8, output [5:0] result...原创 2020-11-06 16:39:20 · 3990 阅读 · 0 评论