1. 出处
xsdk demo : xemacps_example_intr_dma
2. API
/* Memory type */
#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
#define STRONG_ORDERED 0xC02 /* Strongly ordered */
#define DEVICE_MEMORY 0xC06 /* Device memory */
#define RESERVED 0x0 /* reserved memory */
/*****************************************************************************/
/**
* @brief This function sets the memory attributes for a section covering 1MB
* of memory in the translation table.
*
* @param Addr: 32-bit address for which memory attributes need to be set.
* @param attrib: Attribute for the given memory region. xil_mmu.h contains
* definitions of commonly used memory attributes which can be
* utilized for this function.
*
*
* @return None.
*
* @note The MMU or D-cache does not need to be disabled before changing a
* translation table entry.
*
******************************************************************************/
void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
{
u32 *ptr;
u32 section;
section = Addr / 0x100000U;
ptr = &MMUTable;
ptr += section;
if(ptr != NULL) {
*ptr = (Addr & 0xFFF00000U) | attrib;
}
Xil_DCacheFlush();
mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
/* Invalidate all branch predictors */
mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
dsb(); /* ensure completion of the BP and TLB invalidation */
isb(); /* synchronize context on this processor */
}
3. demo
/*
* Buffer descriptors are allocated in uncached memory. The memory is made
* uncached by setting the attributes appropriately in the MMU table.
* The minimum region for which attribute settings take effect is 2MB for
* arm 64 variants(A53) and 1MB for the rest (R5 and A9). Hence the same
* is allocated, even if not used fully by this example, to make sure none
* of the adjacent global memory is affected.
*/
u8 bd_space[0x100000] __attribute__ ((aligned (0x100000)));
Xil_SetTlbAttributes((INTPTR)bd_space, DEVICE_MEMORY);
// or
Xil_SetTlbAttributes((INTPTR)bd_space, NORM_NONCACHE);
4. 注意
Xil_SetTlbAttributes
所配置地址段是从 Addr 开始的1M/2M 空间,由arm核心架构所决定,见demo注释部分描述。