ARM体系平台手册笔记03
异常
中断保存现场:
SUB R14, R14, #4
STMFD SP!, {<other_registers>, R14}
中断返回现场:
LDMFD SP!, {<other_registers>, PC}^
复位
当cpu的Reset input is asserted,ARM processor立即停止当前指令的执行,从而转向下面的指令执行
R14_svc = UNPREDICTABLE value
SPSR_svc = UNPREDICTABLE value
CPSR[4:0] = 0b10011 /* Enter Supervisor mode */
CPSR[5] = 0 /* Execute in ARM state */
CPSR[6] = 1 /* Disable fast interrupts */
CPSR[7] = 1 /* Disable normal interrupts */
CPSR[8] = 1 /* Disable Imprecise Aborts (v6 only) */
CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */
if high vectors configured then
PC = 0xFFFF0000
else
PC = 0x00000000
After Reset, the ARM processor begins execution at address 0x00000000 or 0xFFFF0000 in Supervisor mode with interrupts disabled
复位之后,所有中断禁止使能,ARM处理器以管理员模式从0x0000 0000或者0xffff0000地址处读取代码并执行
未定义的指令异常
当未定义的异常发生时,将执行下面的流程
R14_und = address of next instruction after the Undefined instruction
SPSR_und = CPSR
CPSR[4:0] = 0b11011 /* enter undefined instruction mode*/
CPSR[5] = 0; /* executed in arm state*/
CPSR[7] = 1 /* Disable normal interrupt*/
CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry*/
if high vector configured then
PC = 0xFFFF0004
else
PC = 0x00000004
To return after emulating the undefined instruction use:
MOVS PC,R14
软中断异常
软件中断指令(SWI)进入主管模式以请求特定的主管(操作系统)功能。执行SWI时,执行以下操作:
R14_svc = address of next instruction after the SWI instruction
SPSR_svc = CPSR
CPSR[4:0] = 0b10011 /* Enter Supervisor mode */
CPSR[5] = 0 /* Execute in ARM state */
/* CPSR[6] is unchanged */
CPSR[7] = 1 /* Disable normal interrupts */
/* CPSR[8] is unchanged */
CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */
if high vectors configured then
PC = 0xFFFF0008
else
PC = 0x00000008
return to the instruction following the SWI:
MOVS PC,R14
中断请求异常IRQ
I 标志位,可以控制IRQ中断使能,但是只能在特权模式下改变
R14_irq = address of next instruction to be executed + 4
SPSR_irq = CPSR
CPSR[4:0] = 0b10010 /* Enter IRQ mode */
CPSR[5] = 0 /* Execute in ARM state */
/* CPSR[6] is unchanged */
CPSR[7] = 1 /* Disable normal interrupts */
CPSR[8] = 1 /* Disable Imprecise Data Aborts (v6 only) */
CPSR[9] = CP15_reg1_EEbit /* Endianness 字节序 on exception entry */
if VE==0 then
if high vectors configured then
PC = 0xFFFF0018
else
PC = 0x00000018
else
PC = IMPLEMENTATION DEFINED /* see page A2-26 */
To return after servicing the interrupt, use: //在中断中修复后,重新执行
SUBS PC,R14,#4 //PC = R14 - 4
快速中断请求异常FIQ
F标志位,可以控制FIQ中断使能,但是只能在特权模式下修改
R14_fiq = address of next instruction to be executed + 4
SPSR_fiq = CPSR
CPSR[4:0] = 0b10001 /* Enter FIQ mode */
CPSR[5] = 0 /* Execute in ARM state */
CPSR[6] = 1 /* Disable fast interrupts */
CPSR[7] = 1 /* Disable normal interrupts */
CPSR[8] = 1 /* Disable Imprecise Data Aborts (v6 only) */
CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */
if VE==0 then
if high vectors configured then
PC = 0xFFFF001C
else
PC = 0x0000001C
else
PC = IMPLEMENTATION DEFINED /* see page A2-26 */
To return after servicing the interrupt, use:
SUBS PC, R14,#4
异常优先级
Priority | Exception |
---|---|
Highest 1 | Reset |
2 | Data Abort (including data TLB miss) |
3 | FIQ |
4 | IRQ |
5 | Imprecise Abort (external abort) - ARMv6 |
6 | Prefetch Abort (including prefetch TLB miss) |
Lowest 7 | Undefined instruction 和SWI |
可以看到SWI进入系统请求,优先级最低