I2C学习

I2C：Inter IC

速率：最开始定义最快100kbps，400kbps fastmode。 1998年后3.4Mbit高速。

特征：1.两条总线。2.没有波特率要求，主机产生时钟。3.多主机总线，有仲裁和碰撞检测。

SCL、SDA open-drain，波形sawtooth like——充放电Cp、Rp。长的走线显著增加Cp。标准规定Cp小于400pF，但通过合适的端接电阻，可用于更高的Cp上。

通过连接器连接的板可能串联电阻防止过流。

Rs1、Rs2导致数据接收数据端低电平不为0。

Crosstalk导致spikes，由Cc（cross channel capacitances）产生，can be minimized by短的互连线，效果可以通过增大Rs和Rp来削减。

Master提供clock，标准要求高低电平的最小时间，因此高电容导致长的上升时间导致时钟速率下降。

Clock Stretching：降低I2C速率，在SCL低的时候，总线上任意设备可以将SCL拉低，时间长度不限，这也叫Clock synchronization。

有仲裁机制，可支持多主机，如果冲突，主机会发现某个SDA电平应为高（主机释放了总线）时低，则停止。

 

• The SCL and SDA signals must be sampled by Schmitt Trigger inputs, i.e. with a certain hysteresis.
• Spikes in SCL and SDA signals must be filtered up to a certain amount (only for full speed I2C).
• 否则的话对spick和串扰敏感。

I2C标准定义0.3Vcc为低电平阈值，0.7Vcc为高电平阈值。

问题：1.blocked i2c bus，复位未复位i2c导致设备持续工作。解决方案1：复位后时钟线翻转16次，可跟随一个停止状态。方案2：更安全但复杂，复位后重启所有i2c设备。——i2c是有状态的。

 

地址：7bit和10bit

 

A master transmitter addresses the slave with two address bytes as described above with the RW-Bit=’0′ followed by data bytes from the master. The master receiver transfer is only possible with a Combined Transfer due to the fact that the second address byte can only be transmitted if the RW-Bit of the first address byte is ‘0’. Hence, the start of a master receiver transfer will be the same as a master transmitter transfer followed by a repeated start condition and the first byte of address byte with RW-Bit=’1′ (switching to slave transmitter mode). Please refer to the following master receiver sequence:

* Start condition

* First address byte, RW-Bit=’0′, ACK from the slave

* Second address byte, ACK from the slave

* Repeated start condition (no stop condition!)

* First address byte again, RW-Bit=’1′, ACK from the slave, slave switches to transmit mode

* Slave transmits data bytes, ACK from master

* After the last data byte, the master sends a NACK

* Stop condition