bsb算法_BSB的完整形式是什么？

bsb算法

BSB：背面总线 (BSB: Back-Side Bus)

BSB is an abbreviation of the "Back-Side Bus".

BSB是“ Back-Side Bus”的缩写。

It was an internal computer bus that links the central processing unit to the cache memory of Level 2. In personal computer microprocessor architecture, there are two categories of buses that transmit data towards the computer’s CPU and from a computer's CPU.

它是一条内部计算机总线，将中央处理单元链接到Level 2的高速缓存。在个人计算机微处理器体系结构中，有两类总线向计算机的CPU和计算机的CPU传输数据。

These buses are:

这些巴士是：

1. The frontside bus: the frontside bus transmits data between the CPU and memory controller hub.

   前端总线 ：前端总线在CPU和内存控制器集线器之间传输数据。

2. The backside bus: the backside bus transfers data between the CPU and the computer's secondary cache or level 2 cache.

   后端总线 ：后端总线在CPU和计算机的辅助缓存或2级缓存之间传输数据。

The CPU stores data in the cache memory that is frequently used and requires to be quickly recovered. This enables the CPU of a computer to operate and function more proficiently and powerfully as it can reiterate processes more rapidly.

CPU将数据存储在经常使用且需要快速恢复的高速缓存中。 这使计算机的CPU可以更快速，更有效地重复处理，从而可以更熟练，更强大地运行和运行。

The enhancement in CPU transmission with cache memory was done by backside bus by turning down wide-ranging signals and getting rid of more than enough actions and measures. At the time when the latest processors corresponding to the second-generation Pentium III started to include as a feature on Level 2 cache, the Back-side bus architecture was suspended. At present, the majority of personal computers put together Level 2 and Level 3 cache memory into the CPU, which makes the backside bus outdated. There was no cache memory of Level 2 or Level 3 in the former personal computers. The backside bus was used to access cache memory from the outside as an alternative, which was at that time not much rapid, however in contrast to using RAM through the frontside bus; it is still to a great extent far more rapid.

带有高速缓存存储器的CPU传输的增强是由后端总线通过拒绝大范围的信号并摆脱了足够多的动作和措施来实现的。 当对应于第二代奔腾III的最新处理器开始作为Level 2缓存的功能包括在内时，后端总线体系结构被暂停。 目前，大多数个人计算机将2级和3级缓存存储到CPU中，这使得后端总线已过时。 在以前的个人计算机中，没有二级或三级缓存。 可以使用后端总线从外部访问高速缓存，这在当时并不算快，但是与通过前端总线使用RAM形成对比。 它在很大程度上仍要快得多。

A microprocessor architecture that uses both frontside and backside bus is known as dual-bus architecture or dual independent bus (DIB) architecture. In the architecture of dual-bus, a system using one bus as a frontside that links to the main memory and use an additional bus as a backside that links to the cache memory of Level 2.

同时使用前端总线和后端总线的微处理器架构称为双总线架构或双独立总线(DIB)架构。 在双总线体系结构中，一种系统使用一个总线作为链接到主存储器的前端，而使用附加总线作为链接到第2级高速缓存的后端。

Reference: Back-side_bus

参考： Back-side_bus

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Algo tagged in: Dictionary – 'B'

Algo标签在： 词典 –'B '

翻译自: https://www.includehelp.com/dictionary/bsb-full-form.aspx

bsb算法