计算机vpu处理器_计算机科学组织| 处理器内部通讯

计算机vpu处理器

内部沟通 (Internal communication)

CPU of the computer system communicates with the memory and the I/O devices in order to transfer data between them. However the method of communication of the CPU with memory and I/O devices in different. The CPU may communicate with the memory either directly or through the Cache memory. However, the communication between the CPU and I/O devices is usually implemented with the help of interface. Therefore the internal communication of a processor in the computer can be divided into two major categories:

计算机系统的CPU与内存和I / O设备进行通信,以便在它们之间传输数据。 但是,CPU与内存和I / O设备的通信方法不同。 CPU可以直接或通过高速缓存与内存进行通信。 但是,CPU和I / O设备之间的通信通常是通过接口来实现的。 因此,计算机中处理器的内部通信可以分为两大类:

  1. Processor to memory communication

    处理器到内存的通讯

  2. Processor to I/O devices communication

    处理器到I / O设备的通讯

1)处理器到内存的通讯 (1) Processor to memory communication)

The direct communication between the processor and memory of the computer system is implemented with the help of two registers. Memory Address register (MAR) and Memory Buffer register (MBR). The processor can interact with the memory of the computer system for reading data from the memory as well as for writing data on to the memory. The MAR and MBR register play a very important role in implementing this type of communication. These registers are the special purpose register of the processor.

处理器和计算机系统内存之间的直接通信是借助两个寄存器实现的。 内存地址寄存器(MAR)和内存缓冲区寄存器(MBR)。 处理器可以与计算机系统的存储器交互,以从存储器读取数据以及将数据写到存储器上。 MAR和MBR寄存器在实现此类通信中扮演着非常重要的角色。 这些寄存器是处理器的专用寄存器。

The processor perform the following steps to read the data:

处理器执行以下步骤来读取数据:

  1. First, the processor loads the address of the memory location from where data is in the reader into the MAR register using the address bus.

    首先,处理器使用地址总线将读取器中数据所在的存储位置的地址加载到MAR寄存器中。

  2. After loading the address of the memory location the processor issues the READ control signal through the control bus. The control bus is used to carry the commands issued by the processor and status signals are generated by the various devices in response to these commands.

    加载存储单元的地址后,处理器通过控制总线发出读取控制信号。 控制总线用于承载处理器发出的命令,各种设备响应这些命令生成状态信号。

  3. After receiving the READ control signal the memory loads the data into the MDR register from the location specified in the MAR register using the Data bus.

    收到READ控制信号后,存储器使用数据总线从MAR寄存器中指定的位置将数据加载到MDR寄存器中。

  4. Finally, the data is transferred to the processor.

    最后,数据被传输到处理器。

The processor perform the following steps for writing the data:

处理器执行以下步骤来写入数据:

  1. First, the processor loads the address of the memory location where data is to be written in the MAR register using the address.

    首先,处理器使用该地址将要写入数据的存储位置的地址加载到MAR寄存器中。

  2. After loading the address of the memory location the processor loads the desired data in the MDR register using the Data bus.

    加载存储单元的地址后,处理器使用数据总线将所需的数据加载到MDR寄存器中。

  3. After this, the processor issues the WRITE control signal to the memory using the control bus.

    此后,处理器使用控制总线将WRITE控制信号发送到内存。

  4. Finally, the memory stores the data loaded in the MDR register at the desired memory location.

    最后,存储器将加载到MDR寄存器中的数据存储在所需的存储器位置。

2)处理器到I / O设备的通讯 (2) Processor to I/O devices communication)

The communication between the I/O devices and the processor of the computer system is implemented using an interface unit. In a computer system data is transferred from an input device to the processor and from the processor to an output device.

I / O设备与计算机系统的处理器之间的通信是使用接口单元实现的。 在计算机系统中,数据从输入设备传输到处理器,并从处理器传输到输出设备。

Some steps are performed while transferring data from I/O devices:

从I / O设备传输数据时需要执行一些步骤:

  1. The data is to be transferred is placed on the data bus by the input devices which transfer single bytes of data at a time.

    通过一次传输单个字节数据的输入设备,将要传输的数据放置在数据总线上。

  2. The input devices then issue the data valid signal through the devices control bus to the data register, including that the data is available on the data bus.

    然后,输入设备通过设备控制总线将数据有效信号发布到数据寄存器,包括数据在数据总线上可用。

  3. As the data register now holds the data the For the flog bit of the same register in the interface unit.

    由于数据寄存器现在保存数据,因此接口单元中同一寄存器的flog位。

  4. The processor the now issue an I/O read signal to the data registers in the interface unit.

    现在,处理器向接口单元中的数据寄存器发出I / O读取信号。

  5. The data register then places the data on the data on the data bus connected to the processor of the computer system.

    然后,数据寄存器将数据放在连接到计算机系统处理器的数据总线上的数据上。

Some steps are performed while transferring data to output devices:

在将数据传输到输出设备时执行一些步骤:

  1. The processor laces the data that needs to be transferred on the data bus connected to the data register of the interface unit.

    处理器将需要传输的数据固定在连接到接口单元数据寄存器的数据总线上。

  2. The CPU also places the address of the output devices on the devices address bus.

    CPU还将输出设备的地址放在设备地址总线上。

  3. After placing the address and data on the appropriate buses, CPU issue the I/O write signal, which writes the data on the data register.

    将地址和数据放在适当的总线上之后,CPU发出I / O写信号,该信号将数据写到数据寄存器中。

  4. The data register of the interface unit issue a data accepted signal through the control bus to the processor.

    接口单元的数据寄存器通过控制总线向处理器发出数据接受信号。

  5. The interface unit then places the data stored in the data register on to the data bus connected to the device controller of the output devices.

    然后,接口单元将存储在数据寄存器中的数据放在连接到输出设备的设备控制器的数据总线上。

  6. The output devices then receive the data and send to acknowledgment signal to the processor.

    然后,输出设备接收数据并将确认信号发送到处理器。

翻译自: https://www.includehelp.com/cso/internal-communication-of-processor.aspx

计算机vpu处理器

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