vcs/urg 进行覆盖率coverage merge及部分merge到整体

目录

1.vcs收coverage基本Option

2.相同代码的merge

3.部分merge到整体

3.1 mapfile

3.2 -map使用语法

3.3合并的常见问题

3.3.1 UCAPI-MAP-SHAPEMISMATCH

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coverage相关的用户手册可以在本人的百度云盘中查看Coverage Technology User Guide.pdf

还可以参考gsithxy的博文 [VCS]Condition Coverage收不全的问题及解法 该文给出了vcs收覆盖率的option、merge常见问题、merge常见option

1.vcs收coverage基本Option

Option	description
-cm line+cond+fsm+tgl+branch+assert	line : Enable collecting line or statement coverage cond : Enable collecting condition coverage fsm : Enable collecting FSM coverage tgl : Enable collecting toggle coverage branch : Enable collecting branch coverage assert :  Enable collecting SystemVerilog assertion coverage
-cm_libs yv	yv :Enable collecting coverage source code from Verilog libraries Default doesn't collect coverage of the library files.
-cm_dir $directory_path_name	Specify an name and location for simv.vdb Default is simv.vdb
-cm_log $filename	Specify a log file for monitoring coverage. Default is cm.log. To suppress the log file, you could re-direct the log file to empty path. (ex, -cm_log /dev/null)
-cm_name $testname	Specify a different location for different simulation, used in dsim flow
-cm_hier $filename	Collect particular instances' coverage $filename contents ------------------------------ +/-tree $instance_name [$level] //level number of 0 (or no level number) specifies the entire sub-hierarchy +/-module $module_name
-cm_assert_hier $filename	Collect particular assertion' coverage $filename contents ------------------------------ +/-assert my_assert +/-assert A* +/-assert $instance_name
-cm_line contassign	Specifies enabling line coverage for Verilog continuous assignments.
-cm_tgl portsonly	Only monitor port of toggle coverage, remove net and variables monitor in modules.

2.相同代码的merge

export path := cov_r20111

db_file=$(shell find ${path} -maxdepth 2 -depth -name "simv*")

.PHONY:merge
merge:
        @echo ${db_file}
        urg -full64 -dir ${db_file} -dbname ${path}/merged.vdb  #urg -full64 -dir a.vdb b.vdb c.vdb -dbname xxx.vdb
cov:
        bsub -I verdi -cov -covdir ${path}/merged.vdb

上述命令将path目录下多个simv*.vdb下面的多个覆盖率文件merge成一个叫merge.vdb的文件

3.部分merge到整体

主要参考Coverage Technology User Guide.pdf中mapping coverage一节

项目中经常出现UT覆盖率merge到BT/SST及整芯片的情况。此时需要使用urg的-map命令

3.1 mapfile

-map命令需要mapfile以表明map关系，下图给出的mapfile意思是将module name为My_Ip的在B模块中的两个例化My_Ip1，My_Ip2的覆盖率映射到

A.B.My_Ip1上去。

3.2 -map使用语法

urg -dir base.vdb -dir input.vdb -mapfile file_name

Where, file_name is the mapping configuration file
 

3.3合并的常见问题

3.3.1 UCAPI-MAP-SHAPEMISMATCH

       When merge vdb files of local simulation to whole chip,  you might get the error as following：

“Warning-[UCAPI-MAP-SHAPEMISMATCH] Shape mismatch in mapping”

     导致shape mismatch可能有以下几个原因：

1. Coverage option mismatch;

Make sure the coverage-related options are the same for both vdbs.

For example:if one vdb is compiled with –cm_line contassign and the other isn’t, it will cause shape mismatch;

$vcs_cov_opts .= " -cm_line contassign ";

2. RTL mismatch;

3. Version  mismatch;

4. Tool bug;