verilog uart

module URAT(
RESET,
CLK,
RXD,
EOC,
PDATA,
TXD
);

input  RESET;
input  CLK;
input  RXD;


output EOC;
output[7:0] PDATA;
output TXD;


reg[10:0]  spdata ;
wire       TT;
reg[3:0]   cnt8;
reg        Start;
reg[9:0]   Count; //1024




always @(posedge CLK or negedge RESET or negedge Start)
begin
if( (!RESET) || (!Start) ) Count <= 10'd0 ;
else   Count <= Count + 1'b1 ;
end

//-- Baudrate Select 
assign TT = Count[9]; //-- Count[9] : 9600 ( Default )
//-- Count[8] : 19200 
//-- Count[7] : 38400 

assign EOC = ( cnt8 > 4'd8 )?1'b1:1'b0;//-- End of recevie 


//start
always @(negedge RESET or negedge RXD)
begin
if(!RESET) 
begin
Start <= 1'b0;
end
else if ((cnt8 > 4'd9) && (TT == 1'b0))
begin
Start <= 1'b0;
end
else if (cnt8 == 4'b0)
Start <= 1'b1;
else
Start <= Start;
end 




//-- Recevie 
always @(posedge TT or negedge RESET)
begin :Recevie
//-- Receive data 
if(!RESET)  
spdata <= 11'd0;
else 
spdata[cnt8] <= RXD;
end


always @(posedge TT or negedge RESET or negedge Start)
begin 
if((!RESET) || (!Start))  
cnt8 <= 4'd0;
else if(Start)
cnt8 <= cnt8 + 1'b1;
else
cnt8 <= cnt8 ;
end



assign PDATA = spdata[8:1];
assign TXD   = RXD;

endmodule

module Frequency(
RESET,
GCLKP1,     //-- 50 MHz 
GCLKP2,     //-- 50 MHz  
ClockScan,  
ClockBaud
);

input RESET;
input GCLKP1;
input GCLKP2;


output ClockScan;
output ClockBaud;




//--Clock: 
wire Period1uS; 


//-- GCLK: 1MHz(1uS), 1KHz(1mS), 1Hz(1S)
reg [5:0]Count;
reg [9:0]Count1;


//--Period: 1uS (Period1uS <= GCLKP2; )
always@(negedge RESET or posedge GCLKP1)
begin
if(!RESET)
Count <= 6'b00_0000;
else if(Count > 6'b11_0000)
   Count <= 6'b00_0000;
else
Count <= Count + 1'b1;
end

assign Period1uS = Count[5];


//--Period: 1mS
always@(negedge RESET or posedge Period1uS)
begin
if(!RESET)
Count1 <= 10'b00_0000_0000;
else if(Count1 > 10'b11_1110_0110)
   Count1 <= 10'b00_0000_0000;
else
Count1 <= Count1 + 1'b1;
end


assign ClockScan = Count1[8];




//-- GCLK: 1MHz(1uS), 1KHz(1mS), 1Hz(1S) 
reg [2:0]Count_2;


//--Period: 1uS (Period1uS <= GCLKP1; )
always@(negedge RESET or posedge GCLKP2)
begin
if(!RESET)
Count_2 <= 3'b000;
else 
begin
if(Count_2 > 3'b011)
Count_2 <= 3'b000;
else
Count_2 <= Count_2 + 1'b1;
end
end

assign ClockBaud = (Count_2 < 3'b010)?1'b0:1'b1;

endmodule