design_simply的博客

AXI_BVALID/AXI_BREADY的异步处理AXI_BVALID/AXI_BREADY的异步处理本质上是单比特信号的异步处理，但其对持续总cycle数也需要保持一致。思路是用一个计数器对源时钟域的A_AXI_BVALID&A_AXI_BREADY做计数，然后转换成格雷码，再同步到目标时钟域去，再转换成顺序计数码，在目标时钟域根据B_AXI_BREADY生成对应的B_AXI_...

FPGA Block Mem自动推断首先看一下摘自UG的资料：Xilinx 7 seriesThe block RAM in Xilinx@ 7 series FPGAs stores up to 36 Kbits of data and can be configured as either two independent 18 Kb RAMs, or one 36 Kb RAM...