FPGA Block RAM自动推断

#FPGA Block RAM自动推断

首先看一下摘自UG的资料：

• Xilinx 7 series
• The block RAM in Xilinx@ 7 series FPGAs stores up to 36 Kbits of data and can be
  configured as either two independent 18 Kb RAMs, or one 36 Kb RAM. Each 36 Kb block
  RAM can be configured as a 64K x 1 (when cascaded with an adjacent 36 Kb block RAM),
  32K x 1, 16K x 2, 8K x 4, 4K x 9, 2K x 18, 1K x 36, or 512 x 72 in simple dual-port mode.
  Each 18 Kb block RAM can be configured as a 16K x 1, 8K x2 , 4K x 4, 2K x 9, 1K x 18 or
  512 x 36 in simple dual-port mode.
• 18, 36, or 72-bit wide block RAM ports can have an individual write enable per byte.
  This feature is popular for interfacing to a microprocessor.
• Xilinx ultrascale+
• The block RAM in UltraScale architecture-based devices stores up to 36 Kbits of data and
  can be configured as either two independent 18 Kb RAMs, or one 36 Kb RAM. Each
  block RAM has two write and two read ports. A 36 Kb block RAM can be configured with
  independent port widths for each of those ports as 32K x 1, 16K x 2, 8K x 4, 4K x 9, 2K x 18
  or 1K x 36 (when used as true dual-port (TDP) memory). If only one write and one read port
  are used, a 36 Kb block RAM can additionally be configured with a port width of 512 x 72
  bits (when used as simple dual-port (SDP) memory). An 18 Kb block RAM can be configured
  with independent port widths for each of those ports as 16K x 1, 8K x 2, 4K x 4, 2K x 9 or
  1K x 18 (when used as T DP memory). If only one write and one read port are used, an 18 Kb
  block RAM can additionally be configured with a port width of 512 x 36 bits (when used as
  SDP memory).
• The RAM MODE attribute has been removed. The Vivado@ tools automatically
  determine if a block RAM is used in TDP or SDP m